HDL Specification Generation for Network Packet Processors
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Solution Overview
Problem
The development of network packet processors requires expertise from both protocol and hardware design fields, leading to time-consuming and costly hardware implementation processes.
Innovation Solution
A method for generating a hardware description language (HDL) specification of a network packet processor by determining independent sets of interdependent handlers, assigning actions to concurrent units, and selecting architectures for each set, allowing for rapid generation of HDL specifications that can be implemented efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a hardware implementation of a network packet processor is developed using traditional methods requiring both protocol and hardware design expertise, then the implementation can be customized and optimized, but the development process becomes time-consuming and expensive
Solution Approach 1:
The patent uses template-based HDL code generation where pre-defined templates are instantiated with specific protocol parameters to automatically generate customized hardware implementations. This allows rapid replication of proven designs while adapting to specific protocol requirements, eliminating manual coding while maintaining customization capability
Solution Approach 2:
The patent introduces an intermediate specification language that serves as a bridge between protocol requirements and hardware implementation. This intermediate representation allows automatic translation from protocol specifications to HDL code, eliminating the need for dual expertise while enabling systematic customization through parameterized specifications
2Manufacturing precision
If protocol specifications are manually translated to hardware implementations by experts in both fields, then implementation quality can be ensured, but the cost and complexity of development increase
Solution Approach 1:
The patent implements self-service through automatic HDL code generation from protocol specifications using predefined templates and constraints. The system automatically ensures implementation quality through built-in verification rules and constraints, eliminating the need for manual expert translation while maintaining high implementation quality through systematic code generation
Solution Approach 2:
The patent uses parameterized protocol specifications where protocol details are represented as configurable parameters. By changing these parameters, different protocol implementations are generated automatically, reducing development complexity while maintaining implementation quality through consistent template-based generation and verification
3Productivity
If rapid iteration of protocol specifications and hardware implementations is enabled, then timeliness and quality improvement are achieved, but this requires automated generation tools that increase initial development complexity
Solution Approach 1:
The patent applies preliminary action by pre-defining HDL templates and generation rules before actual protocol implementation is needed. These templates encapsulate common protocol processing patterns and hardware implementation knowledge, enabling rapid iteration once specifications are defined while the heavy lifting of design complexity is resolved in advance
Solution Approach 2:
The patent segments the protocol specification and hardware generation process into independent, parameterized components. This segmentation allows modifications to be made at the specification level without affecting the entire system, enabling rapid iteration through localized changes while the segmentation itself manages the apparent complexity through modular organization
Data Source
AI summary
A method for generating a hardware description language (HDL) specification of a processor of network packets. Independent sets of interdependent handlers are determined from a specification of the handlers for processing the network packets. Either a first pipeline or a cluster of threads is selected for a corresponding architecture for each independent set. The corresponding architecture has one or more concurrent units for each interdependent handler in the independent set. Each concurrent unit is either a stage of the first pipeline or a thread of the cluster. Each action of each interdependent handler in each independent set is assigned to a concurrent unit for the interdependent handler. Each of these actions is also assigned to a stage of a second pipeline for the concurrent unit. The HDL specification of the processor is generated specifying the corresponding architecture for each independent set and the second pipeline for each concurrent unit.