HDL Specification Translator for Graphical Design Automation

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Solution Overview

Problem

Manual conversion of hardware description language (HDL) specifications to graphical design environments is error-prone and time-consuming, requiring extensive HDL code writing and lacking automation, which complicates maintenance and enhancements of circuit designs.

Innovation Solution

A method involving a programmed processor that generates a design graph from an HDL specification, determines matches between HDL modules and library blocks, and translates this into a data model compatible with graphical design environments, reducing the need for manual HDL code writing and enabling automated updates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If circuit designs are created using HDL specifications, then design flexibility and automation potential are improved, but code volume increases making maintenance and enhancements difficult

Engineering Contradiction:
Improvedesign flexibilityVSAvoidcode volume
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates a graphical copy or representation of the HDL circuit design. The system parses HDL code and generates a graphical user interface that visually represents the same circuit design, allowing users to interact with and modify the design graphically rather than through text-based HDL code. This copying approach maintains design flexibility while eliminating the complexity of managing large volumes of HDL code for maintenance.

Inventive Principle:
Principle #26Copying

2Loss of information

If manual conversion from HDL to graphical design environment is performed, then design understanding is improved, but time consumption and error rate increase

Engineering Contradiction:
Improvedesign understandingVSAvoidconversion time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The patent performs preliminary automated parsing and analysis of the HDL code to generate the initial graphical representation. The system pre-processes the HDL specification, identifies circuit components and relationships, and automatically creates the corresponding graphical design environment representation before user interaction begins. This preliminary automated conversion significantly reduces the time and effort required compared to manual conversion while maintaining accurate design understanding.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If HDL code volume increases for mature electronic systems, then design functionality is improved, but error detection and modification become more difficult

Engineering Contradiction:
Improvedesign functionalityVSAvoiderror detection accuracy
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a graphical user interface and design graph as an intermediary between the HDL code and the designer. This intermediary layer provides visual representation of circuit components, connections, and data flow, making it easier to detect errors and understand design functionality. The graphical interface acts as a mediator that translates complex HDL code into visually intuitive representations, improving error detection accuracy without sacrificing design functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10489541B1Hardware description language specification translator
Publication Date: 2019.11.26 XILINX INC
  • US10489541B1 patent drawing
  • US10489541B1 patent drawing
  • US10489541B1 patent drawing

AI summary

Disclosed approaches for translating a hardware description language (HDL) specification include inputting an HDL specification of a circuit design, generating a design graph of the circuit design from the HDL specification, and determining matches between modules of the HDL specification and blocks in a library. The design graph is translated into a data model that describes matching blocks, interfaces from the library, and connections between the blocks based on the matches determined between modules of the HDL specification and blocks of the library. The data model is compatible with a graphical design environment.