HDLC Reception by Pulse-Width Bit Recovery Across Variable Data Rates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing HDLC communication systems rely on dedicated controllers or custom devices, leading to increased costs and limitations in the number of devices that can be daisy chained due to pulse width constraints.
Innovation Solution
A system and method that measures the pulse width of incoming HDLC signals, converts each pulse into a series of bits, and determines the bit rate without relying on a fixed clock rate, allowing adaptable operation over a broad range of data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated HDLC controllers or custom devices are used to implement HDLC protocol, then reliable HDLC communication is achieved, but system cost increases
Solution Approach 1:
The microcontroller is designed to perform multiple functions: it can implement HDLC protocol reception, measure pulse widths, determine bit rates, and reconstruct data packets all within a single general-purpose device. This eliminates the need for dedicated HDLC controllers while maintaining communication reliability.
Solution Approach 2:
The system uses its own internal resources (edge detector/timer circuit, processing unit, memory) to measure pulse widths and determine bit rates without requiring external specialized hardware. The microcontroller serves itself by using built-in capabilities to implement HDLC reception functionality.
2Adaptability or versatility
If devices are connected in a daisy chain configuration, then system expandability is improved, but the number of devices is limited due to pulse width constraints
Solution Approach 1:
Instead of using a fixed clock rate for signal detection, the system dynamically measures the actual pulse widths of incoming signals and adapts its bit rate determination accordingly. This dynamic approach allows the system to accurately capture signals even after they have traversed multiple devices in a daisy chain, where pulse widths may vary due to signal degradation.
Solution Approach 2:
The system changes its operational parameters by measuring actual pulse width values from the incoming signal and using these measurements to determine the bit rate. This parameter adaptation enables the system to maintain reliable communication over extended daisy chains where signal characteristics may change.
3Device complexity
If a fixed clock rate is used for HDLC reception, then simple timing is achieved, but adaptability to different data rates is lost
Solution Approach 1:
The system determines the bit rate by measuring actual pulse widths from the incoming signal rather than relying on a predetermined fixed clock rate. This allows the system to adapt to different data rates while maintaining relatively simple timing logic through automated measurement and calculation.
Data Source
AI summary
A system and method of receiving HDLC communications is disclosed. The system measures the pulse width of the incoming signal and converts each pulse into a series of bits, based on its pulse width. In this way, the reception of the HDLC communication is not dependent on any particular clock rate and is adaptable. The system takes advantages of the fact that the flag is a string of six consecutive bits that are all “1”. Thus, the longest positive pulse width may be used to determine the bit rate. This allows the system to operate over a very broad range of data rates.