HDMI Audio Clock PLL Control for Fast Multi-Rate Locking
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Solution Overview
Problem
Existing audio processors for reproducing audio data through digital interfaces like IEEE1394 and HDMI face challenges in determining the frequency division ratio, leading to increased circuit complexity and longer lock times.
Innovation Solution
An audio processor configuration that includes a sampling frequency information detector, comparison clock frequency divider, analog PLL circuit, and audio clock frequency divider allows for easy determination of the frequency division ratio without increasing circuit scale, reducing lock time, and enabling software-controlled operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a hardware-based section for determining the frequency division ratio is implemented, then the audio processor can handle multiple sampling rates, but the circuit scale increases
Solution Approach 1:
The patent replaces the hardware-based frequency division ratio determination section with a software-based implementation. The sampling frequency information detector, comparison clock frequency divider, and frequency division ratio determination are implemented as software modules that process audio data and calculate the appropriate frequency division ratio dynamically, eliminating the need for complex hardware circuits while maintaining the ability to handle multiple sampling rates
Solution Approach 2:
The patent changes the frequency division ratio parameter dynamically based on the detected sampling frequency information. Instead of using fixed hardware circuits for different sampling rates, the system calculates and adjusts the frequency division ratio parameter in software according to the actual sampling rate requirements, allowing flexible adaptation without hardware reconfiguration
2Reliability
If a hardware-based section for determining the frequency division ratio is implemented, then the audio processor can determine the frequency division ratio, but the lock time increases due to operation time requirements
Solution Approach 1:
The patent implements a sampling frequency information detector that continuously monitors and detects sampling frequency information in advance. This preliminary detection allows the system to prepare the appropriate frequency division ratio before it is actually needed, reducing the lock time when audio data needs to be processed by having the determination already completed or readily available
Solution Approach 2:
The patent replaces the time-consuming hardware-based frequency division ratio determination with a software-based calculation that operates more quickly. The software implementation can compute the frequency division ratio faster than hardware circuits, significantly reducing the lock time while maintaining accurate determination of the correct ratio
3Speed
If a digital PLL circuit is added to reduce lock time, then the locking speed improves, but the circuit complexity increases
Solution Approach 1:
The patent replaces the analog PLL circuit with a digital PLL circuit implementation. The digital PLL uses software-based phase detection and frequency synthesis algorithms that can lock much faster than traditional analog PLL circuits, while the complexity is managed through efficient software algorithms rather than additional hardware components
Solution Approach 2:
The patent implements a dynamic PLL system where the frequency division ratio and other parameters can be adjusted in real-time based on the detected sampling frequency information. This dynamic adaptation allows the PLL to optimize its locking behavior for different sampling rates, achieving fast locking without requiring separate hardware circuits for each rate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the generation of various audio clock signals in a short lock time without increasing circuit complexity, improving the efficiency of audio data reproduction in digital interfaces like HDMI.
Implementation Method 1
an audio clock signal having the same frequency as the sampling rate of transmitted audio data is generated using a phase locked loop (PLL) circuit
Implementation Method 2
thereby generating an audio clock signal obtained by performing frequency multiplication or division on the reference clock signal
Data Source
AI summary
An audio information detector extracts frequency information on audio data from a packet called an ASP in the HDMI standard and outputs the extracted frequency information to a frequency divider as audio information. The frequency divider determines a frequency division ratio based on the audio information, divides the frequency of a PLL clock signal output from an analog PLL circuit by the frequency division ratio and outputs the resultant signal as a comparison clock signal. The analog PLL circuit performs feedback control such that the comparison clock signal and a reference clock signal are synchronized with each other, and generates an audio clock signal obtained by performing frequency multiplication or division on the reference clock signal.