HDMI Clock Trace Layout With Matching Traces for Lower EMI
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Solution Overview
Problem
Electromagnetic interference (EMI) is a significant issue in electronic devices with high-definition multimedia interfaces, particularly due to asymmetric trace layouts of clock pair signal traces, leading to differential-to-common mode conversion and increased EMI.
Innovation Solution
A layout solution for data transmission traces that includes first clock pair signal traces, first data pair signal traces, and a matching trace, where the clock pair signal traces are positioned between the matching and data pair signal traces, with matching traces on opposite sides to equalize parasitic parameters, and use of passive devices to further enhance symmetry and reduce EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If clock pair signal traces are laid out asymmetrically, then layout flexibility is improved, but parasitic parameter consistency deteriorates leading to increased EMI
Solution Approach 1:
The patent applies asymmetry in reverse - it deliberately creates symmetric layout structures (matching traces on both sides of clock pairs) to counteract the natural asymmetry that causes EMI. By introducing symmetric matching traces with equal spacing, the patent balances the parasitic parameters on both sides of differential signal traces, thereby reducing differential-to-common mode conversion while maintaining layout flexibility.
Solution Approach 2:
The patent changes the spacing parameter of traces systematically. It defines first inter-pair trace spacing between matching traces and clock pairs, and second inter-pair trace spacing between clock pairs and data pairs, ensuring these parameters are equal. This parameter control method allows consistent parasitic parameters to be achieved while maintaining design flexibility.
2Length of moving object
If trace length is increased, then signal transmission capability is improved, but EMI increases due to differential-to-common mode conversion
Solution Approach 1:
The patent introduces matching traces as intermediary elements between clock pairs and data pairs. These matching traces act as mediators that balance the electromagnetic field distribution on both sides of the differential signals. By adding these intermediary traces with controlled spacing, the patent reduces the accumulation of parasitic parameter differences that would otherwise increase with trace length, thereby suppressing EMI even in long trace scenarios.
Solution Approach 2:
The patent applies preliminary action by pre-balancing the parasitic parameters through symmetric matching trace placement before signals are transmitted. By establishing equal inter-pair trace spacing from the beginning of the trace layout, the patent prevents the accumulation of parasitic differences that would occur with increased trace length, thereby proactively suppressing EMI generation.
3Object-generated harmful factors
If matching traces are added to balance parasitic parameters, then EMI suppression is improved, but device complexity increases
Solution Approach 1:
The patent applies homogeneity by making the matching traces on both sides of the clock pairs identical in their spacing relationships. The first inter-pair trace spacing is set equal to the second inter-pair trace spacing, creating a homogeneous symmetric structure. This homogeneous design balances parasitic parameters effectively while maintaining relatively simple trace routing patterns that are easy to implement.
4Manufacturing precision
If inter-pair trace spacing is equalized, then parasitic parameter consistency is improved, but layout flexibility is reduced
Solution Approach 1:
The patent resolves the spacing-flexibility contradiction by operating in multiple dimensional aspects. It defines spacing in terms of inter-pair trace spacing (perpendicular to signal flow direction) while allowing flexibility in the longitudinal dimension (along signal flow). This multi-dimensional approach enables precise control of parasitic parameters through spacing equalization while maintaining layout flexibility through independent routing adjustments in other dimensions.
Data Source
AI summary
A layout solution for data transmission trace, a mainboard, and an electronic device are disclosed. In one example, the data transmission trace includes first clock pair signal traces, first data pair signal traces, and a first matching trace. The first clock pair signal traces include a first clock signal trace and a second clock signal trace, and the first clock pair signal traces are configured to transmit a clock signal. The first data pair signal traces include a first data signal trace and a second data signal trace, and the first data pair signal traces are configured to transmit a data signal. The first clock pair signal traces are located between the first matching trace and the first data pair signal traces.