HDMI FRL Data Packing Circuit Buffer Segmentation
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Solution Overview
Problem
HDMI transmitters operating in FRL mode face challenges in efficiently packing data without excessive buffer size, leading to increased costs and potential delays in data transmission due to deviations in real-time and average data rates.
Innovation Solution
A data packing circuit and method that outputs multiple FRL super blocks at fixed unit times, utilizing two smaller buffers and a computation control circuit to map valid data into FRL characters, insert gap characters, and alternate buffer usage for continuous packing, ensuring consistent data rates and reduced time delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single large buffer is used to pack FRL data, then data transmission continuity is improved, but buffer size and cost increase
Solution Approach 1:
The patent divides a single large buffer into multiple smaller buffers (first buffer, second buffer, third buffer, etc.). These buffers work in an alternating fashion, with each buffer processing a portion of the data packing task. This segmentation maintains data transmission continuity while reducing the size requirement of each individual buffer, thereby lowering overall cost.
Solution Approach 2:
The patent implements periodic action by alternating between multiple buffers in a cyclic manner. The data packing circuit switches between buffers at regular intervals (unit times), with each buffer being activated periodically to process FRL data. This periodic alternation ensures continuous data flow while keeping individual buffer sizes small.
2Productivity
If data packing is performed without precise rate control, then processing speed is improved, but data rate deviation increases causing transmission delays
Solution Approach 1:
The patent employs feedback mechanisms through computation control circuits that continuously monitor and count the amount of valid data in each buffer. Based on this feedback information, the system dynamically adjusts the data packing process, inserting gap characters when buffers are nearly full or empty. This feedback control maintains consistent data rates and prevents transmission delays while preserving high processing speed.
Solution Approach 2:
The patent performs preliminary actions by predicting buffer status and proactively inserting gap characters before data rate deviations occur. The computation control circuit anticipates when buffers will become full or empty and takes preventive measures to maintain data rate consistency, avoiding transmission delays before they happen.
Data Source
AI summary
A data packing circuit and a data packing method operated in a high definition multimedia interface (HDMI) transmitter that adopts a fixed rate link mode are provided. The data packing circuit can output a plurality of FRL super blocks at a plurality of unit times. In the data packing method, multiple valid data inputted to the data packing circuit at the (i)th unit time are mapped to a plurality of FRL characters, and the FRL characters are stored to the first or the second buffer. At the same time, an amount of tri-byte of the multiple valid data is counted for determining number and positions for inserting gap characters to form the (i)th FRL super block, which is outputted at the (i+1)th unit time. The numeral ‘i’ is a positive integer.