HDMI FRL SR/SSB Error Correction for Stable Link Synchronization

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Solution Overview

Problem

The HDMI specification lacks error detection mechanisms for Scrambler Reset (SR) and Start of Super Block (SSB) signals, leading to potential bit errors and synchronization issues when the signal-to-noise ratio is low, causing interference such as black screens and flickering lines.

Innovation Solution

Implementing an HDMI Fixed Rate Link (FRL) system with a Scrambler Reset (SR) and Start of Super Block (SSB) correlator, lock detector, predictor, bit error corrector, and detector to correlate, correct, and validate SR/SSB signals, ensuring synchronization and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error detection mechanism is not implemented for SR/SSB signals, then the system complexity remains low, but bit errors occur when signal-to-noise ratio is low causing synchronization issues

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing error detection and correction on SR/SSB signals before they are used for synchronization. The system correlates received SR/SSB signals with expected patterns, detects errors in advance, and corrects them before synchronization operations, preventing synchronization issues before they occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary error detection and correction mechanism between the signal transmission and synchronization processes. The correlator and error correction unit act as intermediaries that process SR/SSB signals, detecting and correcting errors before the signals are used for synchronization, thus isolating the synchronization process from error-prone transmission.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If SR/SSB signals are transmitted without error correction, then the transmission process is simple, but visual interference such as black screens and flickering lines occurs

Engineering Contradiction:
Improveimplementation simplicityVSAvoidvisual interference
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful effect of potential bit errors into a benefit by using error detection and correction mechanisms. Instead of letting errors cause visual interference, the system detects and corrects errors in SR/SSB signals, transforming the potential harm into an opportunity to improve transmission reliability and eliminate visual interference.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If error detection and correction mechanisms are added to SR/SSB signals, then transmission reliability improves, but the device complexity increases

Engineering Contradiction:
Improvetransmission reliabilityVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the error detection and correction process into distinct functional modules: a correlator unit for comparing received signals with expected patterns, an error detection unit for identifying bit errors, and a correction unit for fixing detected errors. This modular segmentation makes the complex error handling process more manageable and implementable.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20260075267A1HDMI FRL correction system and method thereof
Publication Date: 2026.03.12 MEDIATEK INC
  • US20260075267A1 patent drawing
  • US20260075267A1 patent drawing
  • US20260075267A1 patent drawing

AI summary

An HDMI FRL error correction system includes a SR/SSB correlator, an SR/SSB lock detector coupled to the SR/SSB correlator, an SR/SSB predictor coupled to the SR/SSB lock detector, an SR/SSB bit error corrector coupled to the SR/SSB correlator, the SR/SSB lock detector and the SR/SSB predictor, and an SR/SSB detector coupled to the SR/SSB bit error corrector. The SR/SSB correlator is used to correlate an input SR signal to a SR signal or correlate an input SSB signal to a SSB signal and generate a correlation result accordingly. The SR/SSB lock detector is used to set a lock flag according to the correlation result.