HDMI Signal Processing Circuit for Variable Frame Rate Adaptation

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Solution Overview

Problem

Existing HDMI electronic devices face a computing burden when continuously adjusting the interval for transmitting extended metadata packets due to variable frame rates or refresh rates, which affects the accuracy of the frame accurate packet area (FAPA).

Innovation Solution

An electronic device equipped with a decoder circuit, image processing circuit, detection circuit, transmission interval determination circuit, auxiliary data extraction circuit, and encoder circuit, which detects the active display area and vertical synchronization signal to determine the transmission interval for auxiliary data within the FAPA.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software continuously sets the interval for transmitting extended metadata packet to adapt to variable frame rate or refresh rate, then the adaptability to different frame rates is improved, but the computing burden on the electronic device increases

Engineering Contradiction:
Improveadaptability to variable frame rateVSAvoidcomputing burden
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent replaces the software-based continuous interval setting mechanism with a hardware circuit (transmission interval determination circuit) that automatically determines the transmission interval based on detected synchronization signals. This substitution eliminates the computational burden of continuous software adjustments while maintaining adaptability to variable frame rates through hardware-based real-time detection and calculation.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The transmission interval determination circuit autonomously determines the appropriate transmission interval by detecting the vertical synchronization signal and active display area timing without requiring external software control. The circuit self-adjusts to variable frame rates by continuously monitoring the synchronization signals and calculating the interval based on the detected parameters, making the system self-adaptive.

Inventive Principle:
Principle #25Self-service

2Reliability

If the range of FAPA is determined based on variable VBI rows with variable frame rate, then the compliance with HDMI specification is maintained, but the accuracy of transmission interval determination becomes more difficult

Engineering Contradiction:
Improvecompliance with HDMI specificationVSAvoidaccuracy of transmission interval determination
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The detection circuit continuously monitors the vertical synchronization signal and active display area timing, providing real-time feedback to the transmission interval determination circuit. This feedback mechanism ensures that the transmission interval is accurately determined based on the actual frame parameters, maintaining compliance with HDMI specifications even when VBI rows vary with different frame rates.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The detection circuit performs preliminary detection of the vertical synchronization signal and active display area timing before the transmission interval determination is made. By预先 detecting these parameters and establishing the timing reference, the system ensures accurate determination of the FAPA range and transmission interval, maintaining measurement precision despite variable frame rates.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12335506B2Electronic device and associated signal processing method
Publication Date: 2025.06.17 REALTEK SEMICON CORP
  • US12335506B2 patent drawing
  • US12335506B2 patent drawing
  • US12335506B2 patent drawing

AI summary

An electronic device includes a decoder circuit, an image processing circuit, a detection circuit, a transmission interval determination circuit, an auxiliary data extraction circuit, and an encoder circuit. The decoder circuit decodes an input signal to generate the decoded signal. The image processing circuit performs image processing on the decoded signal to generate processed image data. The detection circuit detects timing of an active display area and a vertical synchronization signal in the processed image data to generate a detection result. The transmission interval determination circuit determines a transmission interval of the processed image data according to the detection result. The auxiliary data extraction circuit extracts auxiliary data from the decoded signal. The encoder circuit places the auxiliary data in the transmission interval of the processed image data, and performs encoding to generate an output signal.