HDPCVD Passivation Layer for Semiconductor Die Warpage
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Solution Overview
Problem
Conventional passivation layers in semiconductor devices formed by CVD techniques suffer from temperature mismatch issues during flip-chip bonding, leading to die warpage and bump crack due to inadequate stress relief.
Innovation Solution
A method involving high-density plasma chemical vapor deposition (HDPCVD) to form a compressive oxide layer on the top metal layer, followed by a high compressive silicon nitride layer, with adjustable bias RF to manage stress, effectively addressing stress-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional CVD techniques (PECVD or APCVD) are used to form passivation layers, then the passivation layer can be formed with standard process conditions, but temperature mismatch during flip-chip bonding causes die warpage and bump crack
Solution Approach 1:
The patent changes the deposition parameters by using HDPCVD instead of conventional PECVD or APCVD. This process modification enables the formation of oxide layers with controlled compressive stress, transforming the passivation layer's mechanical properties to compensate for thermal stress mismatch during bonding, thereby preventing die warpage and bump crack
Solution Approach 2:
The patent introduces a multi-layer passivation structure with different stress characteristics. The first passivation layer (oxide) provides compressive stress, while the second passivation layer (nitride) provides tensile stress. This local differentiation of stress properties allows precise control over the overall stress state, enabling the structure to counteract bonding-induced thermal stress
2Device complexity
If a single-layer passivation structure is used, then the manufacturing process is simple, but it cannot provide adequate stress relief
Solution Approach 1:
The patent divides the passivation structure into multiple functional layers: a first passivation layer (oxide) and a second passivation layer (nitride), each with distinct stress properties. This segmentation allows independent optimization of stress characteristics, enabling the composite structure to provide effective stress relief that a single layer cannot achieve
3Reliability
If high compressive stress is applied to prevent warpage, then bonding reliability improves, but the passivation layer may become prone to cracking
Solution Approach 1:
The patent uses the second passivation layer (nitride) with tensile stress to counterbalance the compressive stress of the first passivation layer (oxide). This counterweight approach prevents excessive compressive stress that could cause cracking, while maintaining sufficient net compressive stress to prevent die warpage and bump crack during bonding
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method prevents die warpage and bump crack by achieving substantial compressive strain in the passivation layers, enhancing the reliability of semiconductor devices during bonding processes.
Implementation Method 1
forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process
Implementation Method 2
high-density plasma chemical vapor deposition (HDPCVD) process
Implementation Method 3
forming a second stress-relief layer on the pad and the first stress-relief layer, wherein the second stress-relief layer comprises a high compressive silicon nitride layer
Data Source
AI summary
A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process.