Homogeneous Dual-Rail Logic to Suppress Differential Power Leakage

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Solution Overview

Problem

Differential power analysis (DPA) side-channel attacks pose a significant threat to embedded system security and crypto-hardware, with existing countermeasures like WDDL suffering from high energy and area overheads while still being vulnerable to attacks, and other methods like randomization and masking countermeasures experiencing performance degradation.

Innovation Solution

The implementation of homogeneous dual-rail logic (HDRL) circuits, which consist of a primary cell and an identical complementary cell, ensuring balanced power consumption and resistance to DPA attacks with lower energy overhead compared to WDDL, without requiring a pre-charge step or modifying the original circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If WDDL dual-rail logic is used to resist DPA attacks, then DPA attack resistivity is improved, but energy consumption increases by more than 100% and area overhead exceeds 2×

Engineering Contradiction:
ImproveDPA attack resistivityVSAvoidenergy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent uses identical duplicate cells (copying the same cell type) instead of WDDL's complementary cell pairing. Each primary cell is paired with an identical duplicate cell that performs the same logic function, ensuring matched switching behavior and power consumption characteristics while avoiding the energy overhead of WDDL's complementary cell approach

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent employs homogeneous cell pairing where identical cell types are paired together (e.g., AND with AND, OR with OR) rather than heterogeneous pairing. This homogeneity ensures that paired cells have identical switching characteristics and power consumption profiles, making them indistinguishable to DPA attackers while maintaining lower energy consumption

Inventive Principle:
Principle #33Homogeneity

2Reliability

If WDDL dual-rail logic is used to resist DPA attacks, then DPA attack resistivity is improved, but area overhead increases by more than 100%

Engineering Contradiction:
ImproveDPA attack resistivityVSAvoidarea overhead
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent uses identical duplicate cells (copying the same cell type) instead of WDDL's complementary cell pairing. Each primary cell is paired with an identical duplicate cell that performs the same logic function, ensuring matched switching behavior and power consumption characteristics while avoiding the energy overhead of WDDL's complementary cell approach

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent employs homogeneous cell pairing where identical cell types are paired together (e.g., AND with AND, OR with OR) rather than heterogeneous pairing. This homogeneity ensures that paired cells have identical switching characteristics and power consumption profiles, making them indistinguishable to DPA attackers while maintaining lower energy consumption

Inventive Principle:
Principle #33Homogeneity

3Reliability

If randomization techniques and masking countermeasures are used, then DPA attack difficulty is increased, but performance degradation occurs

Engineering Contradiction:
ImproveDPA attack resistivityVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent uses simple, lightweight countermeasures based on identical cell pairing that can be applied at standard cell level without complex overhead. The approach uses basic identical duplicate cells rather than complex randomization or masking circuits, providing effective DPA protection with minimal performance impact and low implementation cost

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

4Reliability

If Sense Amplifier Based Logic (SABL) is used, then power imbalance is minimized, but design cost and time increase prohibitively

Engineering Contradiction:
Improvepower balanceVSAvoiddesign cost and time
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent uses simple, lightweight countermeasures based on identical cell pairing that can be applied at standard cell level without complex overhead. The approach uses basic identical duplicate cells rather than complex randomization or masking circuits, providing effective DPA protection with minimal performance impact and low implementation cost

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent applies the countermeasure at the standard cell level by pairing individual identical cells, allowing modular implementation and reuse across the entire circuit. This segmented approach enables systematic application of the technique throughout the design without requiring full-custom implementation, reducing both design cost and time

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8395408B2Homogeneous dual-rail logic for DPA attack resistive secure circuit design
Publication Date: 2013.03.12 RGT UNIV OF CALIFORNIA
  • US8395408B2 patent drawing
  • US8395408B2 patent drawing
  • US8395408B2 patent drawing

AI summary

Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks.