Hardware Data Transport Circuitry Reduced Signaling Buffer Management
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Solution Overview
Problem
Existing data transceiver systems, particularly those using the SDIO interface, face inefficiencies due to time-consuming firmware-based exchanges of bitmaps for buffer slot management, which overwhelm hardware data transport circuitry and slow down data transfer rates.
Innovation Solution
Implementing a reduced signaling approach using start and stop signals, such as 'near-empty' and 'near-full' signals, to manage buffer slots in hardware data transport circuitry, eliminating the need for constant bitmap updates and interrupts, thereby simplifying the transport controller functions without altering the media access controller or hardware data transport circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If firmware-based bitmap exchange is used for buffer slot management, then data transfer compatibility with SDIO interface is maintained, but data transfer rate decreases and signaling overhead increases
Solution Approach 1:
The patent changes the signaling parameters from detailed bitmap exchanges to simplified threshold-based start/stop signals. Instead of exchanging complete buffer status bitmaps, the system uses near-empty and near-full threshold signals to control data transfer, reducing signaling overhead while maintaining buffer management functionality
Solution Approach 2:
The patent extracts only the essential control functions from the firmware-based bitmap exchange mechanism. By taking out just the buffer status threshold detection and transfer control functions, the system eliminates complex bitmap processing while retaining the core buffer management capability through hardware-based start/stop signaling
2Productivity
If firmware instructions are used for buffer management, then flexibility in handling different buffer scenarios is maintained, but processing time increases and efficiency decreases
Solution Approach 1:
The patent substitutes firmware-based software control with hardware-based automatic control. The hardware data transport circuitry automatically monitors buffer status and generates start/stop signals based on near-empty and near-full thresholds, eliminating the time-consuming firmware instruction execution cycle while maintaining buffer management flexibility
Solution Approach 2:
The hardware data transport circuitry performs self-service by automatically detecting buffer status and controlling data transfer without firmware intervention. The circuitry monitors its own buffer slots and autonomously generates control signals, eliminating the need for external firmware management and reducing processing delays
3Measurement precision
If constant bitmap updates are implemented, then accurate buffer status tracking is maintained, but hardware data transport circuitry becomes overwhelmed and transfer performance decreases
Solution Approach 1:
Instead of implementing complete and constant bitmap updates, the patent applies partial action by using only the critical threshold points (near-empty and near-full) to control data transfer. This selective monitoring maintains sufficient buffer status tracking accuracy while avoiding the performance degradation caused by exhaustive bitmap exchanges
Data Source
AI summary
A wireless data transceiver includes a media access controller (MAC) that receives an inbound packet from an air interface and to buffer that packet for transport to a host, and receives an outbound packet and transfers that packet to the air interface. A host interface receives the inbound packet from the MAC and transfers the inbound packet to the host, and receives the outbound packet from the host for transfer to the MAC. Transport controller circuitry (TCC), including processing circuitry configured to execute instructions, manages the transceiver. Hardware data transport circuitry (HDTC) for transporting packets in either direction between the MAC and the host interface includes a buffer memory having a plurality of slots. The TCC or HDTC issues a start or stop signal to the host interface causing the HDTC and the host interface to begin or end transfer of data between the buffer memory and the host interface.