Homomorphic Encryption Chiplet Architecture for Yield and Speed
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Solution Overview
Problem
The existing homomorphic encryption (HE) technologies face challenges with large chip sizes due to yield limitations in micro-processing technology and increased complexity, leading to high manufacturing costs and low yields, especially when implementing HE accelerators using application-specific integrated circuits (ASICs).
Innovation Solution
A multi-chiplet architecture is proposed, utilizing a substrate with through-silicon vias (TSVs) and interposers to connect core and memory chiplets in a ring structure, enabling efficient data transmission and parallel operation of number-theoretic transform (NTT) and multiply-accumulate (MAC) modules, which accelerates HE operations while reducing manufacturing costs and increasing yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If HE accelerators are implemented using ASICs to enhance performance, then HE operation speed is improved, but chip size increases and manufacturing yield decreases
Solution Approach 1:
The patent divides the HE accelerator into multiple independent chiplets (compute chiplets and memory chiplets) that can be manufactured separately on smaller substrates with higher yield, then interconnected through an interposer. This segmentation allows each chiplet to be produced within acceptable yield limits while collectively achieving the required computational performance.
Solution Approach 2:
The patent transitions from a planar 2D chip architecture to a 3D stacked architecture using an interposer with TSVs. Memory chiplets are vertically stacked above compute chiplets, enabling higher density and performance without proportionally increasing the footprint area, thus maintaining manufacturing feasibility.
2Manufacturing precision
If chip size is reduced to improve manufacturing yield, then manufacturing cost decreases and yield increases, but HE operation performance deteriorates
Solution Approach 1:
The patent merges multiple small chiplets (compute chiplets and memory chiplets) into a unified HE accelerator system through the interposer infrastructure. While each individual chiplet remains small for high yield, their collective functionality achieves the required HE operation performance through parallel processing and high-speed inter-chiplet communication.
Solution Approach 2:
The interposer acts as an intermediary substrate that enables high-speed communication between compute chiplets and memory chiplets. It provides TSV-based vertical interconnects and routing infrastructure, allowing small chiplets to achieve system-level performance comparable to or exceeding large monolithic designs.
3Productivity
If more operators are added to HE accelerators to enhance performance, then HE operation capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the computational operators into distributed NTT modules across multiple compute chiplets. Each chiplet contains a subset of operators that can operate independently and in parallel, reducing the complexity burden on any single chiplet while achieving aggregate high performance through coordinated operation.
Data Source
AI summary
An electronic device includes a substrate, an interposer attached to a top of the substrate and comprising a plurality of through-silicon vias (TSVs), a plurality of core chiplets attached to a top of the interposer, and a plurality of memory chiplets attached to the top of the interposer, wherein each of the plurality of core chiplets comprises a number-theoretic transform (NTT) module.