Semiconductor Layout With Head Cell Power Gating Between Hard Macros

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Solution Overview

Problem

The increasing complexity of semiconductor devices makes manual layout design difficult, and existing semi-custom methods require larger standard cells, complicating the design process.

Innovation Solution

A semiconductor device design method that includes a head cell for power gating between hard macros, with ending cells arranged to prevent overlap, allowing for efficient use of standard cell areas and reducing layout area, and a method for fabricating the device using optical proximity correction and photomasks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Extent of automation

If standard cells are used in semi-custom layout design, then design automation is improved, but layout area increases due to larger cell sizes required for high integration

Engineering Contradiction:

Improvelayout design automationVSAvoidlayout area

Core Design Contradiction:

Extent of automationVSArea of stationary object

Solution Approach 1:

The layout is divided into standard cell areas and hard macro areas, allowing different design approaches for different regions. Standard cells provide automation while hard macros optimize critical functions, reducing overall layout area through strategic segmentation of the chip design.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If chip complexity increases, then functionality is improved, but manual layout design becomes increasingly difficult

Engineering Contradiction:

Improvechip functionalityVSAvoidmanual layout design

Core Design Contradiction:

Adaptability or versatilityVSEase of operation

Solution Approach 1:

A head cell is introduced as an intermediary component between hard macros to manage power supply distribution. This intermediary structure simplifies the layout design process by providing a standardized interface for power gating, reducing the complexity of manual design despite increased chip functionality.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If head cell is placed in standard cell area, then power gating functionality is achieved, but overlap with ending cells may occur increasing layout complexity

Engineering Contradiction:

Improvepower gating functionalityVSAvoidlayout complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The head cell position is predetermined and reserved in the standard cell area during the design phase, before ending cells are placed. This preliminary allocation of space ensures power gating functionality is achieved while preventing overlap with ending cells, thereby avoiding increased layout complexity.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11869884B2Semiconductor devices, methods of designing layouts of semiconductor devices and methods of fabricating semiconductor devices

Publication Date: 2024.01.09 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.