Header-Corrected EDC Circuit for Lower Optical Disc Bandwidth
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Solution Overview
Problem
Conventional optical disc encoding systems require large bandwidth due to the need for the EDC generator to read and write entire sectors for error detection, which is inefficient and wasteful.
Innovation Solution
An EDC generating circuit that includes a memory unit, an EDC generating module, a header generator, and an EDC correcting circuit, allowing for independent processing of main data and headers, reducing the need to read all data from the memory unit and minimizing bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the EDC generator reads and writes entire sectors to generate error detection codes, then the EDC can be generated correctly according to the conventional structure, but the bandwidth required is excessively large and the processing efficiency is low
Solution Approach 1:
The patent divides the sector data into two independent parts: main data and header. The EDC generation process is segmented into two stages: first generating EDC based on main data only, then correcting it using header information. This segmentation allows the system to process only necessary data portions rather than reading entire sectors, thereby improving processing efficiency while maintaining EDC correctness.
Solution Approach 2:
The patent performs preliminary EDC generation based on main data before the header is fully processed. The initial EDC is generated in advance using only the main data portion, and then corrected later using the header. This preliminary action eliminates the need to wait for complete sector reading, significantly reducing bandwidth requirements and improving processing speed.
2Reliability
If the EDC generator reads the whole sector to generate EDC, then the EDC includes complete error detection information, but the bandwidth consumption is high and data access time is increased
Solution Approach 1:
The patent segments the EDC generation process into two phases: initial EDC generation from main data, and subsequent correction using header information. This segmentation enables the system to generate a functional EDC without reading the entire sector, reducing data access time while maintaining error detection completeness through the correction phase.
Solution Approach 2:
The system performs preliminary EDC generation using only main data before header processing is complete. This preliminary EDC, while not final, provides immediate error detection capability. The complete error detection is achieved later by correcting this preliminary EDC with header-based adjustments, thereby eliminating unnecessary data access time.
3Adaptability or versatility
If the transmission interface and header generator operate independently, then the system architecture is more flexible and modular, but the EDC generation requires reading all data from memory increasing bandwidth usage
Solution Approach 1:
The patent segments the EDC generation responsibility between the independent transmission interface/header generator and the EDC correcting circuit. The EDC generating module (operating independently with main data) produces initial EDC, while the EDC correcting circuit (receiving header from the independent header generator) performs correction. This segmentation maintains architectural flexibility while improving bandwidth efficiency by avoiding redundant data reading.
Data Source
AI summary
An EDC generating circuit includes a memory unit, an EDC generating module, a header generator and an EDC correcting circuit. The EDC generating module, which is coupled to the memory unit, is used for generating a first EDC according to at least one main data, and for storing the first EDC to the memory unit. The header generator, which is coupled to the memory unit, is used for generating a header according to header information. The EDC correcting circuit, which is coupled to the memory unit, is used for reading the first EDC from the memory unit and for correcting the first EDC according to the header to generate a second EDC.


