Network Switch Header-Payload Split to Mask Intra-Packet Delay
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Solution Overview
Problem
Ethernet network switches experience increased latency due to intra-packet delays and underruns, which can lead to packet drops and reduced competitiveness in the market.
Innovation Solution
A network switch design that includes a first data path to separate and bypass payload cells from header processing, a traffic manager with separate control and data paths for early control signal transmission, and a second data path for temporary storage and jitter compensation to manage timing and delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If internal processing complexity of switches is increased to handle more packets, then processing capability is improved, but internal delays increase resulting in higher overall latency
Solution Approach 1:
The patent segments the packet processing into separate paths: a first data path for payload cells and a second data path for header processing. This segmentation allows payload cells to bypass the complex header processing stage, reducing internal delays while maintaining processing capability for headers.
Solution Approach 2:
The patent introduces a bypass route as an intermediary path that allows payload cells to skip the header processing queue. This intermediary mechanism decouples the timing between payload and header processing, reducing the impact of internal processing complexity on overall latency.
2Reliability
If the last stage waits for sufficient time after SOP arrival to account for intra-packet delays, then packet transmission reliability is improved, but latency increases
Solution Approach 1:
The patent implements preliminary action by having the first data path transmit payload cells ahead of the header processing completion. The bypass route prepares and transmits payload cells in advance, so they arrive at the output before the header processing is complete, eliminating the need to wait for the full intra-packet delay period.
Solution Approach 2:
The patent allows payload cells to skip the traditional sequential processing queue by using the bypass route. This rushing through mechanism enables payload cells to bypass the header processing delay entirely, achieving faster transmission while maintaining reliability through coordinated timing with the second data path.
3Loss of time
If payload cells bypass header processing, then latency is reduced, but timing synchronization between payload and header becomes difficult
Solution Approach 1:
The patent implements feedback mechanisms where the second data path monitors the processing status of headers and provides control signals to the first data path. This feedback loop ensures that payload cells bypassing the header processing are properly synchronized and reassembled in the correct sequence, managing timing complexity through active coordination.
Solution Approach 2:
The patent uses the bypass route and its associated control logic as an intermediary that coordinates between the fast payload path and the slower header processing path. This intermediary manages the timing synchronization by controlling when payload cells are transmitted and ensuring they are properly reassembled with their corresponding headers.
Data Source
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AI summary
A network switch (100) comprises a first data path (10) configured to separate a header from a payload of an incoming packet, the first data path (10) is characterized by a reduced latency for cells of the payload without a first processing delay associated with the header in the second data path (30). The network switch (100) also includes a controller configured with a first control path to transmit a control bus carrying control signals for individual cells and a second control path to transmit a data bus carrying the header and the payload, wherein the control bus is transmitted before the data bus. The network switch (100) also includes a second data path (30) configured to receive the control bus and the data bus separately, and to store the cells temporarily for managing the timing of the cells and handling a second processing delay associated with the header in the second data path (30) before transmitting the packet.