Headerless Memory Frame Protocol for High-Speed Data Transfer
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Solution Overview
Problem
Current memory devices face challenges in achieving high reliability, low latency, and low power consumption while maintaining scalability and cost-effectiveness, especially for applications requiring high bandwidth such as terabytes per second data transfer rates.
Innovation Solution
The implementation of a frame protocol that eliminates headers in data frames to maximize data transfer rates, using a frame training procedure to identify frame boundaries and generate a frame clock, allowing the memory device to synchronize with the host device without overhead signaling, and reconfiguring the frame structure based on the type of interposer used to couple the host device with the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If headers are included in data frames for synchronization and boundary identification, then reliability of data transfer is improved, but data transfer rate and productivity deteriorate due to overhead signaling
Solution Approach 1:
The patent extracts and removes the header portion from the data frame structure. Instead of including traditional headers with synchronization patterns and boundary markers, the invention uses a headerless frame format where the payload itself contains the necessary information for identification and synchronization, thereby eliminating overhead and maximizing data transfer efficiency
Solution Approach 2:
The patent performs preliminary actions during a training phase before actual data transfer. During this training phase, the memory device and host device establish synchronization and identify frame boundaries using training patterns. Once synchronized, the system can operate in headerless mode for the duration of the active session, achieving high-speed transfer without repeated overhead signaling
2Reliability
If complex frame structures with overhead signaling are used to ensure reliable synchronization, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent removes the complex header structure entirely from the data frame. Instead of using separate synchronization fields, address fields, and control fields in the header, the invention embeds the necessary synchronization information within the payload data itself, significantly simplifying the overall frame structure while maintaining synchronization reliability
Solution Approach 2:
The payload data serves multiple functions simultaneously: it carries the actual information being transferred and also contains the synchronization patterns and boundary markers needed for frame identification. This self-service approach eliminates the need for separate header structures, reducing device complexity while maintaining reliable synchronization
3Productivity
If high data transfer rates are achieved through optimized frame protocols, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent removes overhead signaling elements from the data frame structure. By eliminating headers and using a headerless frame format, the system reduces the total number of bits that need to be transmitted and processed, thereby reducing power consumption while maintaining high data transfer rates for the actual payload information
Solution Approach 2:
The patent establishes continuous synchronization during the active session through the training phase, allowing data transfer to proceed without interruption or repeated overhead signaling. This continuous operation mode maintains high productivity while reducing power consumption compared to systems that require periodic re-synchronization with overhead frames
Data Source
AI summary
Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.