Hearing Aid Clock Synchronization Circuit
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Solution Overview
Problem
Hearing aid devices face issues with audio artifacts such as 'click' or 'pop' sounds when the clock frequency changes, leading to undesirable audio quality due to potential phase errors in the internal oscillator, especially during clock throttling events.
Innovation Solution
A synchronization circuit monitors the state of the output subsystem and synchronizes the clock frequency change based on the state information to reduce or eliminate audio artifacts, ensuring coherent PWM output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to meet higher processing requirements, then the processing capability is improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic clock frequency adjustment by monitoring the sigma-delta modulator state and adjusting the clock frequency accordingly. The clock frequency is increased only when processing demands require it, and decreased when demands are lower, making the system's operational characteristics changeable based on real-time conditions rather than operating at a fixed high frequency
Solution Approach 2:
The patent changes the clock frequency parameter dynamically based on the processing load and modulator state. By adjusting this key parameter according to actual needs, the system achieves variable processing capability and power consumption levels, allowing optimization between performance and energy usage
2Use of energy by moving object
If the clock frequency is changed in real-time to reduce power consumption, then the power consumption is reduced, but audio artifacts such as clicks or pops occur
Solution Approach 1:
The patent uses feedback by monitoring the state of the sigma-delta modulator and using this information to control clock frequency changes. The system continuously observes the modulator output state and adjusts the clock frequency based on this feedback, ensuring changes occur only when they will not disrupt the PWM output coherence
Solution Approach 2:
The patent performs preliminary checks of the modulator state before changing the clock frequency. By evaluating the current state in advance and only proceeding with frequency changes when conditions are favorable, the system prevents audio artifacts from occurring in the first place rather than correcting them afterward
3Productivity
If the internal oscillator frequency is adjusted to meet processing demands, then the processing demand is met, but phase errors occur in the PWM output signal
Solution Approach 1:
The system monitors the sigma-delta modulator state as feedback to determine when clock frequency changes are safe to perform. This feedback mechanism ensures that frequency adjustments are synchronized with the modulator's operational state, maintaining PWM output coherence even during transitions
Solution Approach 2:
The patent uses the sigma-delta modulator state as an intermediary condition that mediates between the clock frequency adjustment and the PWM output. By using this intermediate state information to control the frequency changes, the system ensures that transitions occur only when they will not corrupt the output signal
Data Source
AI summary
In one embodiment, a method and system includes: synchronizing the timing of the change of a clock frequency based on the state of an output subsystem for driving an output transducer.