Hearing Device Clock Synchronization via Buffer Skew Feedback
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Solution Overview
Problem
The mismatch in system clock frequencies between wirelessly connected hearing devices leads to sample overflow and underflow events, degrading the perceptual quality of binaural beamformed audio signals due to inaccurate timing relationships, which existing methods fail to address effectively using compact, inexpensive, and low-power circuits.
Innovation Solution
A method to adjust the system clock frequency of a slave hearing device by detecting overflow and underflow events in buffers, using frequency adjustments in steps of 0.5 to 5 ppm to match the master device's frequency, combined with sample realignment to conceal these events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If separate crystal-based clock generators are used in each hearing device, then device independence and compact size are achieved, but clock frequency mismatch and skew occur due to production tolerances and temperature drift
Solution Approach 1:
The patent implements a feedback mechanism where the slave device continuously monitors buffer overflow and underflow events caused by clock skew, and automatically adjusts its clock frequency in response. The controller receives information about timing errors and modifies the clock signal parameters to minimize skew, creating a closed-loop system that maintains synchronization despite temperature drift and aging effects
Solution Approach 2:
The patent dynamically changes clock frequency parameters to compensate for drift. The slave device adjusts its clock frequency in small increments (e.g., ±10 ppm) based on observed timing errors, allowing the system to adapt to changing environmental conditions while maintaining synchronization without requiring larger, more expensive crystal oscillators
2Measurement precision
If higher precision clock generators are used to reduce clock skew, then timing accuracy improves, but device size, cost, and power consumption increase
Solution Approach 1:
The patent uses low-cost, small-footprint clock generators with limited precision (e.g., ±20-30 ppm crystal oscillators) and compensates for their imperfections through software-based frequency adjustment. Rather than investing in high-precision hardware, the system employs inexpensive clock sources and corrects their drift through adaptive algorithms, reducing both component cost and power consumption
Solution Approach 2:
The patent replaces hardware-based precision timing solutions with software-based clock frequency adjustment mechanisms. Instead of using mechanically precise crystal oscillators or atomic clocks, the system uses digital signal processing and firmware-controlled frequency synthesis to achieve the required timing accuracy, thereby reducing power consumption and device size
3Device complexity
If clock frequency mismatch is left uncorrected, then device complexity remains low, but sample overflow and underflow events occur, degrading audio quality
Solution Approach 1:
The patent performs preliminary clock synchronization during the device pairing and initialization phase. The master and slave devices exchange timing information and pre-adjust their clock frequencies before actual audio streaming begins, preventing buffer overflow and underflow events from occurring in the first place and maintaining audio quality without requiring complex real-time correction mechanisms
Data Source
AI summary
The present disclosure relates in one aspect to methods of adjusting a second system clock frequency of a slave or second device to a first system clock frequency of a first device connectable thereto via a unidirectional or bidirectional wireless data communication link so to reduce clock skew between the first and second system clock frequencies.