Heat Spreader Power Delivery for Stacked Semiconductor Chips
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Solution Overview
Problem
Stacked semiconductor chip designs face challenges in providing adequate electrical interfaces, thermal management, and delivering electrical power efficiently, often limiting bandwidth due to the majority of interconnects being used for power/ground in conventional designs.
Innovation Solution
The use of a heat spreader with an inductive or capacitive power transfer circuit to deliver electrical power to the semiconductor chips, allowing for power transfer from the heat spreader to the chips, thereby reducing the need for power/ground interconnects and increasing signal bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interconnect design is used where majority of interconnects are dedicated to power/ground, then reliable power delivery is achieved, but signal bandwidth is limited
Solution Approach 1:
The patent extracts the power delivery function from the traditional interconnect structure by introducing a dedicated power delivery coil that couples magnetically with the chip's power coil. This separation allows interconnects to be primarily used for signals while power is delivered through the magnetic coupling mechanism, thereby increasing signal bandwidth without compromising power delivery reliability
Solution Approach 2:
The patent introduces a magnetic field as an intermediary between the power delivery coil and the chip's power coil. This magnetic coupling mechanism serves as a mediator that transfers power without requiring direct electrical contact through interconnects, thus freeing up interconnect resources for signal transmission while maintaining reliable power delivery
2Adaptability or versatility
If stacked chip architecture is implemented to increase integration density, then device functionality is improved, but thermal management becomes more difficult
Solution Approach 1:
The patent addresses thermal management in stacked chips by introducing a thermal management layer that extends the heat dissipation path into the vertical dimension. This layer provides additional thermal pathways that conduct heat away from the stacked chips, effectively managing temperature without compromising the vertical integration architecture
3Reliability
If more interconnects are used for power/ground to ensure adequate power delivery, then power supply stability is improved, but the number of available signal interconnects decreases
Solution Approach 1:
The patent extracts the power delivery function from the interconnect structure by implementing a separate magnetic coupling-based power delivery system. This allows the interconnect configuration to be optimized for signals while power is delivered through the dedicated magnetic coupling mechanism, thereby maintaining power supply stability without increasing interconnect complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient power delivery to stacked semiconductor chips, reducing the number of interconnects required for power/ground and increasing the bandwidth available for signals, while effectively managing heat through the heat spreader.
Implementation Method 1
Some conventional integrated circuits, such as microprocessors, generate sizeable quantities of heat that must be transferred away to avoid device shutdown or damage. The lid serves as both a protective cover and a heat transfer pathway.
Implementation Method 2
The use of a heat spreader with an inductive or capacitive power transfer circuit to deliver electrical power to the semiconductor chips
Implementation Method 3
The use of a heat spreader with an inductive or capacitive power transfer circuit to deliver electrical power to the semiconductor chips
Data Source
AI summary
Various chip stack power delivery circuits are disclosed. In one aspect, an apparatus is provided that includes a stack of semiconductor chips that has an uppermost semiconductor chip and a lowermost semiconductor chip. A heat spreader is positioned on the uppermost semiconductor chip. A power transfer circuit is configured to transfer electric power from the heat spreader to the uppermost semiconductor chip.