Heavy-Hex Qubit Layout in a Rectilinear Tile Grid
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Solution Overview
Problem
Heavy-hex physical qubit layouts in quantum computing systems are spatially inefficient, leading to wasted chip real estate and increased fabrication costs, while maintaining the desirable heavy-hex connection topology for quantum error correcting codes.
Innovation Solution
Mapping a heavy-hex qubit connection topology to a rectilinear physical qubit layout by tessellating qubit tiles with irregular shapes, such as duck or cow shapes, within a rectilinear grid to densely pack qubits without losing the connection topology efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a heavy-hex physical qubit layout is used to maintain the heavy-hex connection topology, then quantum error correcting capabilities are improved, but chip real estate is wasted and fabrication costs increase
Solution Approach 1:
The qubit layout is divided into multiple qubit tiles, each with a specific shape (e.g., hexagonal, square, or irregular), that can be independently arranged. These tiles are then assembled into a larger rectilinear grid structure, allowing the heavy-hex connection topology to be maintained within each tile while the overall layout becomes space-efficient and rectangular, eliminating wasted chip real estate.
Solution Approach 2:
The invention transitions from a purely two-dimensional heavy-hex tiling arrangement to a composite structure that combines 2D qubit tiles with inter-qubit connection buses that extend in multiple dimensions. This allows the connection topology to be preserved while the physical layout adopts a rectilinear grid that packs qubits more efficiently, reducing the overall area required.
2Reliability
If a heavy-hex physical qubit layout is used to maintain connection topology, then quantum error correcting capabilities are improved, but fabrication costs increase
Solution Approach 1:
By segmenting the qubit layout into standardized qubit tiles that can be manufactured using standard fabrication processes, the invention simplifies manufacturing. These modular tiles can be produced independently and then assembled, reducing the complexity and cost of fabrication compared to manufacturing a single large heavy-hex structure.
Solution Approach 2:
The invention changes the geometric parameters of the qubit layout from a purely heavy-hex configuration to a hybrid structure with rectilinear boundaries. This parameter change allows the layout to be manufactured using standard semiconductor fabrication techniques that are optimized for rectangular geometries, thereby reducing fabrication costs while maintaining the heavy-hex connection topology through the internal arrangement of qubits within and between tiles.
3Area of stationary object
If qubit tiles are tessellated in a rectilinear layout, then chip real estate is reduced, but the connection topology may be compromised
Solution Approach 1:
The qubit system is segmented into multiple tiles, each maintaining the heavy-hex connection topology internally. The tiles are then arranged in a rectilinear grid and connected through inter-qubit connection buses that bridge adjacent tiles. This segmentation allows each local region to preserve the desired topology while the global arrangement achieves space efficiency.
Solution Approach 2:
Inter-qubit connection buses serve as intermediaries between adjacent qubit tiles. These buses maintain the heavy-hex connection topology by providing controlled coupling between qubits in different tiles, ensuring that the topological properties are preserved across the entire system while allowing the tiles to be arranged in a space-efficient rectilinear layout.
Data Source
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AI summary
Systems and techniques that facilitate mapping a heavy-hex qubit connection topology to a rectilinear physical qubit layout are provided. In various embodiments, a device can comprise a qubit lattice on a substrate. In various aspects, the qubit lattice can comprise one or more first qubit tiles. In various cases, the one or more first qubit tiles can have a first shape. In various instances, the qubit lattice can further comprise one or more second qubit tiles. In various cases, the one or more second qubit tiles can have a second shape. In various aspects, the one or more first qubit tiles can be tessellated with the one or more second qubit tiles. In various embodiments, the qubit lattice can exhibit a rectilinear physical layout. In various embodiments, the one or more first qubit tiles tessellated with the one or more second qubit tiles can form a heavy-hex qubit connection topology in the rectilinear physical layout of the qubit lattice. In various embodiments, one of the one or more first qubit tiles can have twelve qubits and twelve interqubit connection buses. In various cases, one of the one or more second qubit tiles can have twelve qubits and twelve interqubit connection buses. In various embodiments, adjacent qubit tiles in the heavy-hex qubit connection topology can share three qubits. In various embodiments, a qubit tile in the heavy-hex qubit connection topology can be adjacent to four qubit tiles having a different shape than the qubit tile. In various cases, the qubit tile can be adjacent to two qubit tiles having a same shape as the qubit tile.