Enhancement-Mode HEMT With Recessed Gate And Fixed Charge Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Typical high electron mobility transistors (HEMTs) are normally 'on' devices, making them unsuitable for many applications due to current conduction before circuitry is fully powered, and existing methods for creating enhancement-mode HEMTs face challenges such as high current leakage and variability in manufacturing, particularly in controlling the etching depth of the barrier layer.
Innovation Solution
The development of an enhancement-mode HEMT device with a heterojunction comprising a channel layer and a barrier layer, where intervening layers with materials like aluminum nitride are used to enhance fixed charge in non-gated regions, and a gate dielectric like aluminum oxide is employed to suppress leakage, allowing for precise control of threshold voltage without the need for precise etching or heavy p+ doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heavy p+ doping is used to create enhancement-mode HEMT, then the device can be turned off, but high current leakage occurs resulting in increased power consumption and heat generation
Solution Approach 1:
The patent applies local quality by creating a recessed gate structure only in specific regions where enhancement-mode operation is needed, while maintaining the barrier layer integrity in other areas. This localized modification allows the device to achieve enhancement-mode characteristics without the harmful effects of heavy doping across the entire structure.
Solution Approach 2:
The patent transitions from a planar gate structure to a three-dimensional recessed gate structure. By etching the barrier layer to create a recess, the gate electrode can be positioned at different depths, providing an additional dimensional parameter to control threshold voltage and achieve enhancement-mode operation without heavy doping.
2Measurement precision
If precise etching of the barrier layer is performed to create recessed gate structure, then threshold voltage can be controlled, but manufacturing precision deteriorates due to wafer variations making it difficult to control etching depth
Solution Approach 1:
The patent performs preliminary action by forming the recessed gate structure during the epitaxial growth process itself, rather than relying on subsequent etching steps. The barrier layer is grown with a predefined thickness variation that automatically creates the desired recess depth, eliminating the need for precise post-growth etching and reducing sensitivity to wafer variations.
Solution Approach 2:
The patent replaces the mechanical/chemical etching process with an epitaxial growth process to create the recessed structure. Instead of removing material through etching, the structure is built up through controlled deposition, which is less sensitive to wafer variations and provides better manufacturing precision.
3Reliability
If the barrier layer is etched to form recessed gate structure, then enhancement-mode operation is achieved, but device complexity increases and suitability for large-scale manufacturing decreases
Solution Approach 1:
The patent merges the recessed gate structure formation with the existing barrier layer growth process. By integrating the recess creation into the epitaxial growth step, the patent eliminates separate etching and re-growth operations, reducing process complexity while maintaining enhancement-mode operation.
Solution Approach 2:
The patent applies self-service by designing the barrier layer with inherent thickness variations that automatically create the recessed structure during growth. The process self-regulates to produce the desired geometry without requiring complex external control mechanisms or multiple processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in an enhancement-mode HEMT with consistent transistor characteristics across a wafer, reduced gate leakage, and enhanced conductivity in non-gated regions, making it suitable for large-scale manufacturing and improving power and frequency performance.
Implementation Method 1
A two-dimensional electron gas (2DEG) forms in the channel layer of a group III-N HEMT device due to a polarization induced charge at the channel-barrier layer interface
Implementation Method 2
A negatively-biased voltage may be applied to the gate electrode to deplete the 2DEG and thereby turn off the device
Data Source
AI summary
A high electron mobility transistor (HEMT) device with enhanced conductivity in the transistor's non-gated access regions and a method for making the HEMT device is disclosed. In one embodiment, the HEMT device includes a heterojunction comprising a barrier layer formed on a channel layer. One or more intervening layers comprising a material suitable for increasing a fixed charge at the heterojunction is formed on a substantially planar surface of the barrier layer opposite the channel layer in the non-gated access region.