Height-Controlled Sidewall Interconnects for 3D Semiconductor Stacks
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Solution Overview
Problem
The miniaturization of semiconductor elements poses challenges in manufacturing high-density interconnection structures, particularly in stacking multiple layers, where traditional methods struggle to provide flexible and efficient interconnections with low resistance and high bandwidth.
Innovation Solution
A semiconductor device with a sidewall interconnection structure is developed, utilizing an electrical isolation layer and a conductive structure formed through a mask layer etching process, allowing for lateral interconnections among stacked elements, reducing photolithography steps, and enabling three-dimensional configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional interconnection methods are used for stacked elements, then manufacturing process is simpler, but interconnection density and flexibility are insufficient
Solution Approach 1:
The patent transitions from planar interconnections to three-dimensional sidewall interconnections. Conductive structures are formed on the sidewalls of element stacks, enabling vertical and lateral connections simultaneously. This dimensional change allows multiple elements to be interconnected through their sidewalls, dramatically increasing interconnection density without requiring additional lateral space.
Solution Approach 2:
The manufacturing process is segmented into separate stages: element stack formation followed by independent sidewall interconnection formation. The mask layer is selectively patterned to define different conductive structures at different heights and positions. This segmentation allows flexible interconnection design while maintaining manufacturing efficiency through standardized process modules.
2Manufacturing precision
If more photolithography steps are used to form conductive structures, then manufacturing precision is improved, but manufacturing cost and process time increase
Solution Approach 1:
The mask layer serves multiple functions: it defines the pattern of conductive structures, acts as an etching mask for selective removal of conductive material, and enables height control through its thickness. This multi-functionality reduces the number of separate lithography and patterning steps required, improving throughput while maintaining precision through the mask layer's inherent properties.
Solution Approach 2:
The patent controls the height and position of conductive structures by adjusting mask layer parameters such as thickness, material composition, and pattern geometry. By changing these parameters, different interconnection configurations can be achieved without requiring additional lithography steps, thus maintaining precision while improving manufacturing efficiency.
3Area of stationary object
If lateral interconnection area is reduced to minimize device footprint, then area efficiency is improved, but interconnection flexibility and bandwidth are reduced
Solution Approach 1:
The patent utilizes the vertical dimension by forming conductive structures on sidewalls at different heights. This allows interconnections to be established without requiring additional lateral area, as connections are made through vertical access to sidewall surfaces. The three-dimensional configuration maintains high bandwidth by providing multiple parallel conduction paths while minimizing footprint.
Solution Approach 2:
The sidewall interconnection structure nests within the existing element stack geometry. Conductive structures are formed on the external surfaces of element stacks, utilizing the vertical space already defined by the stacked elements. This nesting approach enables dense interconnections without requiring additional lateral space beyond the element stack boundaries.
4Ease of manufacture
If semiconductor device manufacturing and metallization stack manufacturing are integrated, then process coordination is improved, but manufacturing flexibility and cost are worsened
Solution Approach 1:
The patent separates semiconductor device manufacturing into distinct stages: element stack formation and subsequent sidewall interconnection formation. The metallization stack (interconnection structure) is formed as an independent process stage after the semiconductor elements are complete. This segmentation allows each process to be optimized independently and enables flexible integration of different semiconductor technologies with various interconnection architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates efficient electrical connections with low resistance and high bandwidth, allowing for increased integration density and separation of semiconductor device manufacturing from metallization stack manufacturing, while reducing manufacturing costs.
Implementation Method 1
using the mask layer as an etching mask to selectively etch the conductive material layer
Data Source
AI summary
A method of manufacturing a semiconductor device includes: providing an element stack on a carrier substrate; forming an interconnection structure connecting the element stack laterally in an area on the carrier substrate adjacent to the element stack, wherein the interconnection structure includes an electrical isolation layer and a conductive structure in the electrical isolation layer; and controlling a height of the conductive structure in the interconnection structure, so that at least a part of components to be electrically connected in the element stack are in contact and therefore electrically connected to the conductive structure at the corresponding height. Forming the conductive structure includes: forming a conductive material layer in the area; forming a mask layer covering the conductive material layer; patterning the mask layer into a pattern corresponding to the conductive structure; and using the mask layer as an etching mask to selectively etch the conductive material layer.