Helium-Based Dual-Layer Spacer Etching for Semiconductor Gate Control

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Solution Overview

Problem

Current spacer etching techniques in semiconductor manufacturing cause substrate damage and struggle with uniformity and control, especially as critical dimensions scale down, leading to issues with gate oxide/polysilicon gate configurations and the transition to high K-metal gate configurations.

Innovation Solution

A method involving a dual-layer spacer etching process using helium-based etching gases to control the etching rate and selectivity, with a main etching operation followed by an over etching operation, optimizing the gate stack configuration and reducing substrate damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional Ar-based etching gases are used for spacer etching, then the etching process can be performed, but substrate damage occurs and etching uniformity deteriorates

Engineering Contradiction:
Improveetching uniformityVSAvoidsubstrate damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent changes the etching gas composition from conventional Ar-based gases to a specific mixture containing CF4 (40-80 sccm), CHF3 (20-60 sccm), and He (100-300 sccm). This parameter change in gas composition reduces substrate damage while improving etching uniformity by controlling the etching rate and reducing ion bombardment effects.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Helium acts as an intermediary gas in the etching mixture, moderating the etching process by reducing direct ion bombardment on the substrate while maintaining effective etching of the spacer material. The He gas mediates between the reactive fluorine-containing gases and the substrate, reducing damage.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If the etching rate is slowed down to improve uniformity, then etching uniformity improves, but the gate height reduction becomes insufficient

Engineering Contradiction:
Improveetching uniformityVSAvoidgate height
Core Design Contradiction:
Manufacturing precisionVSLength of moving object

Solution Approach 1:

The patent optimizes the etching gas flow rates and composition to achieve a balanced etching rate that simultaneously provides good uniformity and sufficient gate height reduction. The specific CF4/CHF3/He ratio allows controlled etching that removes adequate material while maintaining uniformity.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the oxide layer thickness is reduced to improve gate control, then gate control capability improves, but oxygen plasma penetrates through and causes silicon loss

Engineering Contradiction:
Improvegate control capabilityVSAvoidsilicon loss
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

Helium gas serves as a protective intermediary that reduces the penetration depth and energy of oxygen plasma through the thin oxide layer, preventing excessive silicon loss while allowing the etching process to proceed effectively.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the etching gas composition to include helium, which modifies the plasma characteristics and reduces the damaging effects on the thin oxide layer and underlying silicon, enabling processing of thinner gate oxides without excessive material loss.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces substrate damage, enhances gate control capability, and improves driving current by achieving a dual-layer complex spacer configuration with precise control over the etching process, optimizing threshold voltage and reducing the equivalent oxide thickness (EOT).

Implementation Method 1

etching the second dielectric layer and the first dielectric layer sequentially with an etching gas containing helium to form a second spacer and a first spacer

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS8728948B2Method of manufacturing semiconductor device
Publication Date: 2014.05.20 INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
  • US8728948B2 patent drawing
  • US8728948B2 patent drawing
  • US8728948B2 patent drawing

AI summary

A method of manufacturing a semiconductor device is disclosed. The method may comprise: forming a gate stack on a substrate; depositing a first dielectric layer and a second dielectric layer sequentially on the substrate and the gate stack; and etching the second dielectric layer and the first dielectric layer sequentially with an etching gas containing helium to form a second spacer and a first spacer, respectively. According to the method disclosed herein, a dual-layer complex spacer configuration is achieved, and two etching operations where the etching gas comprises the helium gas are performed. As a result, it is possible to reduce damages to the substrate and also to reduce the process complexity. Further, it is possible to optimize a threshold voltage, effectively reduce an EOT, and enhance a gate control capability and a driving current.