HEMT Back Contact Structure for Precise Single-Mask Trenching
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Solution Overview
Problem
Existing HEMT devices face challenges in manufacturing due to low etch selectivity between semiconductor heterostructure and source metal layer, leading to difficult post-etch treatments, integration issues, and high manufacturing costs, along with mechanical stress causing cracks and dislocations during wafer dicing.
Innovation Solution
The HEMT device incorporates external and internal seal rings with controlled trench formation using a single etch mask, ensuring precise removal of epitaxial multilayer and substrate materials, and optimized contact regions for improved electrical connection and reduced manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single lithography mask is used to form both the trench through the back metal layer and the trench through the semiconductor heterostructure, then the manufacturing process is simplified, but the etch selectivity between GaN and source metal layer becomes problematic leading to poor manufacturing precision
Solution Approach 1:
A sacrificial layer is introduced as an intermediary between the back metal layer and the semiconductor heterostructure. This sacrificial layer serves as a selective etch stop that allows the trench to be formed through the back metal layer and sacrificial layer without significantly etching the source metal layer or semiconductor heterostructure, thereby achieving precise trench formation using a single lithography mask.
Solution Approach 2:
The original single trench formation process is segmented into two distinct etching steps: first etching through the back metal layer and sacrificial layer, then separately etching through the semiconductor heterostructure. This segmentation allows each etching step to be optimized with appropriate selectivity, resolving the precision issue while maintaining the simplified single-mask approach.
2Reliability
If post-etch treatments are implemented to inhibit corrosion of the source metal layer, then the reliability of the source metal layer is improved, but the manufacturing process complexity and costs increase
Solution Approach 1:
The sacrificial layer is deposited and patterned beforehand, before the source metal layer is formed. This preliminary action creates a protective configuration where the sacrificial layer physically separates and protects the source metal layer from corrosive etchants during subsequent processing steps, eliminating the need for additional post-etch corrosion inhibition treatments.
3Ease of manufacture
If the semiconductor heterostructure is grown on a silicon or silicon carbide wafer, then the manufacturing cost is reduced, but lattice mismatch causes mechanical stress leading to cracks and dislocations during wafer dicing
Solution Approach 1:
The problematic epitaxial multilayer is selectively removed (taken out) from regions surrounding the active area of the HEMT device. This extraction eliminates the source of mechanical stress in those regions, preventing crack and dislocation propagation during wafer dicing while maintaining the cost advantage of using silicon or silicon carbide substrates.
Solution Approach 2:
The wafer is functionally segmented into an active area where the epitaxial multilayer is retained for device operation, and a non-active peripheral area where the epitaxial multilayer is removed to relieve mechanical stress. This spatial segmentation allows the device to benefit from both low-cost substrates and high reliability during dicing.
4Reliability
If external and internal seal rings are formed to prevent crack propagation during dicing, then the device reliability is improved, but additional manufacturing steps are required reducing productivity
Solution Approach 1:
The formation of seal rings and the removal of the epitaxial multilayer for stress relief are merged into a single integrated process step. By combining these functions, the patent achieves both crack prevention and stress relief without requiring separate manufacturing steps, thereby maintaining high productivity while improving device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances manufacturing yield and reduces costs while minimizing mechanical stress, ensuring reliable electrical connections and increased reliability of the HEMT device.
Implementation Method 1
The operation of a heterostructure-based transistor device is based on the formation of a two-dimensional charge carrier (electrons) gas inside a semiconductor heterostructure, at the interface between two different semiconductor materials, generally AlGaN/GaN layers.
Implementation Method 2
the formation of the two-dimensional carrier gas inside the active area is electrostatically modulated by a gate region
Implementation Method 3
both the semiconductor heterostructure 3 and the source metal layer 6 are etched using chlorine-based etchant solutions
Data Source
Figure 1~2
Figure 3
Figure 4A
AI summary
For manufacturing a device (20) based on heterostructure, a work body (100) is provided having a wafer (130) and an epitaxial multilayer (31) that extends on the wafer along a direction (Z) from a front surface of the wafer up to an upper surface (31A). To form an active area (23), a conduction region (50A) of conductive material is formed on the epitaxial multilayer. To form a contact region (60) for biasing the first conduction region: a front trench (61) is formed in the work body starting from the upper surface (31A) towards the back surface of the wafer, up to a contact surface (65); a conductive region (50B) is formed inside the front trench, on the contact surface, and in electrical contact with the first conduction region; a back trench (62) is formed in the work body starting from the back surface (130B) towards the upper surface up to the contact surface; and a back metallization layer (70) is formed on the back surface of the wafer and inside the back trench, on the contact surface.