HEMT Barrier Layer Doping for Lower Dynamic On-Resistance
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Solution Overview
Problem
The efficiency of silicon-based switching devices in power conversion systems is limited, prompting the need for improved semiconductor devices with enhanced dynamic on-resistance (Dynamic Ron) to overcome material limitations.
Innovation Solution
A semiconductor device structure incorporating a channel layer, lower and upper barrier layers with different impurity concentrations, a gate semiconductor layer, and source and drain configurations, optimized for high electron mobility transistor (HEMT) design, where the lower barrier layer defines a recess and has a varying thickness to enhance 2DEG formation and reduce traps, thereby improving dynamic on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If silicon-based switching devices are used in power conversion systems, then the device structure is simple and manufacturing is mature, but the efficiency is limited due to material limitations
Solution Approach 1:
The patent employs a heterojunction structure composed of multiple semiconductor materials with different bandgaps and electron mobilities. Specifically, it uses a low-bandgap semiconductor layer (e.g., GaN) combined with a high-bandgap semiconductor layer (e.g., AlN or AlGaN), creating a composite material system that leverages the advantages of each material to achieve both high efficiency and controlled complexity
Solution Approach 2:
The invention introduces barrier layers with specifically engineered impurity concentrations at critical locations within the device structure. The lower barrier layer has a first impurity concentration while the upper barrier layer has a second impurity concentration, creating local variations in electrical properties that optimize electron transport and reduce losses without requiring complete restructuring of the entire device
2Loss of energy
If a heterojunction structure with barrier layers is implemented to overcome silicon limitations, then efficiency improves, but device complexity increases
Solution Approach 1:
The device is divided into functionally distinct layers including a channel layer, lower barrier layer, upper barrier layer, and gate electrode structure. Each layer is optimized for its specific function: the channel layer provides electron transport, the lower barrier layer forms a first heterojunction interface, and the upper barrier layer forms a second heterojunction interface, allowing complex functionality to be achieved through modular layering
Solution Approach 2:
The patent systematically varies impurity concentrations across different layers to optimize device performance. The lower barrier layer contains a first impurity concentration while the upper barrier layer contains a second impurity concentration, creating a gradient that controls electron distribution and reduces traps. This parameter optimization allows efficient electron transport without requiring excessive structural complexity
3Reliability
If impurity concentrations are optimized in barrier layers to reduce traps, then dynamic on-resistance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies concrete impurity concentration ranges for each barrier layer to achieve optimal performance while maintaining manufacturability. The lower barrier layer is doped with a first impurity concentration within a specific range, and the upper barrier layer is doped with a second impurity concentration within a specific range, providing clear manufacturing targets that balance performance optimization with fabrication feasibility
Solution Approach 2:
Different impurity concentrations are applied to different layers based on their specific functional requirements. The lower barrier layer receives a first impurity concentration optimized for its interface with the channel layer, while the upper barrier layer receives a second impurity concentration optimized for its interface with the gate structure, allowing each region to be optimized independently within achievable manufacturing tolerances
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed semiconductor device structure achieves improved dynamic on-resistance and reduced gate leakage current, enabling more efficient current control and operation as a high electron mobility transistor (HEMT) with a normally off characteristic.
Implementation Method 1
research on a high electron mobility transistor (HEMT) using a heterojunction structure of a compound semiconductor has been actively conducted
Implementation Method 2
optimized for high electron mobility transistor (HEMT) design, where the lower barrier layer defines a recess and has a varying thickness to enhance 2DEG formation
Implementation Method 3
a lower barrier layer on the channel layer and including first impurities, an upper barrier layer on the lower barrier layer and including second impurities at a greater concentration than a concentration of the first impurities
Implementation Method 4
optimized for high electron mobility transistor (HEMT) design, where the lower barrier layer defines a recess and has a varying thickness to enhance 2DEG formation and reduce traps
Data Source
AI summary
A semiconductor device includes a channel layer, a lower barrier layer on the channel layer and including first impurities, an upper barrier layer arranged on the lower barrier layer and including second impurities having a concentration greater than a concentration of the first impurities, a gate electrode on the upper barrier layer, a gate semiconductor layer between the upper barrier layer and the gate electrode, and a source and a drain that are on the channel layer and are spaced apart from each other.