HEMT Buffer Superlattice Structure for Lattice Defect Blocking

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Solution Overview

Problem

Existing semiconductor devices with gallium nitride-based materials face issues of lattice mismatch and thermal expansion coefficient mismatch, leading to lattice defects that affect device reliability and performance.

Innovation Solution

The introduction of a superlattice layer arranged in both horizontal and vertical directions within the buffer layer, composed of alternately stacked heteromaterials, to prevent the upward transmission of lattice defects and improve structural compatibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If gallium nitride based materials are used to form high electron mobility transistors, then high power and high frequency performance is achieved, but lattice defects occur due to lattice mismatch and thermal expansion coefficient mismatch

Engineering Contradiction:
Improvehigh power performanceVSAvoiddevice reliability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The buffer layer is segmented into multiple sub-layers with different compositions (AlN, GaN, AlGaN) arranged in a superlattice structure. This segmentation allows gradual transition of lattice constants and thermal expansion coefficients, effectively reducing mismatch defects while maintaining the high power performance of GaN-based HEMTs

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A composite buffer layer structure is created by combining multiple semiconductor materials (AlN, GaN, AlGaN) with different lattice constants and thermal expansion coefficients. This composite structure mitigates the harmful effects of lattice mismatch and thermal expansion mismatch between the substrate and the active GaN layer, improving device reliability without sacrificing power performance

Inventive Principle:
Principle #40Composite materials

2Speed

If gallium nitride based materials are used to form high electron mobility transistors, then high frequency performance is achieved, but lattice defects occur due to lattice mismatch and thermal expansion coefficient mismatch

Engineering Contradiction:
Improvehigh frequency performanceVSAvoiddevice reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The buffer layer is segmented into multiple sub-layers with different compositions (AlN, GaN, AlGaN) arranged in a superlattice structure. This segmentation allows gradual transition of lattice constants and thermal expansion coefficients, effectively reducing mismatch defects while maintaining the high frequency performance of GaN-based HEMTs

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A composite buffer layer structure is created by combining multiple semiconductor materials (AlN, GaN, AlGaN) with different lattice constants and thermal expansion coefficients. This composite structure mitigates the harmful effects of lattice mismatch and thermal expansion mismatch between the substrate and the active GaN layer, improving device reliability without sacrificing frequency performance

Inventive Principle:
Principle #40Composite materials

3Ease of manufacture

If a conventional buffer layer is used, then fabrication is simple, but lattice defects extend or diffuse upwardly affecting device performance

Engineering Contradiction:
Improvefabrication simplicityVSAvoiddefect control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The buffer layer is divided into multiple thin sub-layers (AlN, GaN, AlGaN) with alternating compositions arranged in a superlattice structure. This segmentation provides gradual lattice constant transition, effectively blocking defect propagation while remaining compatible with conventional MOCVD fabrication processes

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The buffer layer structure transitions from a conventional single-layer or simple multi-layer design to a superlattice structure with alternating layers in the vertical dimension. This dimensional complexity in the growth direction provides gradual lattice transition and defect blocking, while maintaining compatibility with standard horizontal epitaxial growth processes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances device reliability and performance by laterally diverting lattice defects, preventing dislocation and fractures, thereby optimizing the integrity and functionality of high electron mobility transistors.

Implementation Method 1

to prevent lattice defects from extending or diffusing upwardly. Thus, the semiconductor device of the present disclosure may significantly improve the defects of gallium nitride based material layers caused by lattice mismatch

Methodology Applied
Scientific EffectLattice mismatch:

Implementation Method 2

caused by lattice mismatch and/or thermal expansion coefficient mismatch

Methodology Applied
Scientific EffectThermal expansion coefficient mismatch: Thermal Expansion

Implementation Method 3

A two-dimensional electron gas (2DEG) may be generated by the piezoelectricity property of the GaN-based materials, and the switching velocity may be enhanced because of the higher electron velocity and the higher electron density of the two-dimensional electron gas

Methodology Applied
Scientific EffectPiezoelectricity: Piezoelectric Effect

Data Source

PatentUS20260020304A1Fabricating Method of Semiconductor Device
Publication Date: 2026.01.15 UNITED MICROELECTRONICS CORP
  • US20260020304A1 patent drawing
  • US20260020304A1 patent drawing
  • US20260020304A1 patent drawing

AI summary

The present disclosure provides a fabricating method of a high electron mobility transistor device, including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.