HEMT Contact Hole Layout for Concurrent Gate and Source/Drain Formation
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Solution Overview
Problem
Conventional methods for fabricating high electron mobility transistors (HEMTs) are complex and costly due to the need for separate photolithography, etching, and metal deposition processes to define gate and source/drain contact holes.
Innovation Solution
A HEMT design that includes a group III-V channel layer, a passivation layer, and a group III-V barrier layer, where a gate structure and source/drain electrodes are formed concurrently using the same photolithography and etching processes, with the passivation layer covering the channel and barrier layers, and the gate electrode conformally covering the passivation layer, simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate photolithography, etching, and metal deposition processes are used to define gate and source/drain contact holes, then the transistor structure can be properly formed, but the fabrication process complexity and cost increase
Solution Approach 1:
The patent combines the formation of gate contact holes and source/drain contact holes into a single photolithography and etching process step. By using a unified mask pattern that defines both types of contact holes simultaneously, the method eliminates the need for separate processing steps, thereby reducing fabrication process complexity while maintaining the precision required for proper contact hole definition
Solution Approach 2:
The photolithography mask and etching process are designed to perform multiple functions: defining both gate contact holes and source/drain contact holes in one operation. This multi-functional approach allows a single process step to accomplish what traditionally required multiple separate steps, reducing overall process complexity without sacrificing manufacturing precision
2Manufacturing precision
If separate photolithography, etching, and metal deposition processes are used to define gate and source/drain contact holes, then the transistor structure can be properly formed, but the fabrication cost increases
Solution Approach 1:
The patent combines the formation of gate contact holes and source/drain contact holes into a single photolithography and etching process step. By using a unified mask pattern that defines both types of contact holes simultaneously, the method eliminates the need for separate processing steps, thereby reducing fabrication process complexity while maintaining the precision required for proper contact hole definition
Solution Approach 2:
The photolithography mask and etching process are designed to perform multiple functions: defining both gate contact holes and source/drain contact holes in one operation. This multi-functional approach allows a single process step to accomplish what traditionally required multiple separate steps, reducing overall process complexity without sacrificing manufacturing precision
Data Source
AI summary
A method of fabricating a HEMT includes the following steps. A substrate having a group III-V channel layer, a group III-V barrier layer, a group III-V gate layer, and a gate etch stop layer disposed thereon is provided. A passivation layer is formed to cover the group III-V barrier layer and the gate etch stop layer. A gate contact hole and at least one source/drain contact hole are formed in the passivation layer, where the gate contact hole exposes the gate etch stop layer, and the at least one source/drain contact hole exposes the group III-V channel layer. In addition, a conductive layer is conformally disposed on a top surface of the passivation layer and in the gate contact hole and the at least one source/drain contact hole.