Dopant Holding Layer for HEMT Defect Prevention

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Solution Overview

Problem

The doping process in high electron mobility transistors (HEMTs) often introduces defects and damages the devices, leading to performance issues and reduced yield, as dopants can diffuse and affect surrounding components during subsequent processes.

Innovation Solution

Incorporating a dopant holding layer, such as aluminum nitride or indium gallium nitride, with a thickness between 0.5 nm and 5 nm, to form a stable alloy with dopants, preventing diffusion and protecting underlying regions from damage during etching and other processes, thereby improving thermal stability and yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a doping process is used to improve HEMT performance, then electron mobility and breakdown voltage are improved, but defects are introduced and device damage occurs

Engineering Contradiction:
ImproveHEMT performanceVSAvoiddefects and device damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A dopant holding layer is introduced as an intermediary between the compound semiconductor layer and surrounding structures. This layer selectively binds dopants (such as magnesium) to prevent their diffusion into adjacent regions, thereby eliminating the harmful effects of dopant migration while preserving the beneficial doping effects in the channel region

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The harmful function of dopant diffusion is extracted and isolated by confining dopants within the dopant holding layer through selective binding. The beneficial doping function is maintained in the compound semiconductor layer while the harmful diffusion is prevented by removing mobile dopants from the system

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If dopants are used to enhance device performance, then electrical characteristics are improved, but dopant diffusion affects surrounding components

Engineering Contradiction:
Improveelectrical characteristicsVSAvoiddopant diffusion
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The dopant holding layer acts as a mediator that selectively interacts with dopants, binding them through chemical affinity (e.g., magnesium oxide formation) to prevent diffusion into surrounding components while allowing the doped region to maintain its electrical functionality

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If conventional doping is applied, then device performance is enhanced, but yield is reduced due to process damage

Engineering Contradiction:
Improvedevice performanceVSAvoidyield
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The dopant holding layer is formed in advance before subsequent processing steps. This preliminary structure prevents dopant diffusion during etching and other manufacturing processes, protecting the device from damage and improving yield without requiring additional repair steps

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The dopant holding layer effectively fixes dopants in place, reducing thermal diffusion and protecting underlying components, enhancing the reliability and yield of HEMT devices by preventing dopant-induced defects and leakage.

Implementation Method 1

reducing thermal diffusion

Methodology Applied
Scientific EffectThermal diffusion: Diffusion

Data Source

PatentUS10700189B1Semiconductor devices and methods for forming the same
Publication Date: 2020.06.30 VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
  • US10700189B1 patent drawing
  • US10700189B1 patent drawing
  • US10700189B1 patent drawing

AI summary

A semiconductor device is provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a dopant holding layer, a source/drain pair, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer and the dopant holding layer are disposed over the barrier layer. The source/drain pair are disposed over the substrate and on both sides of the compound semiconductor layer. The gate is disposed over the compound semiconductor layer.