HEMT Enhancement Layer for Current and Power Optimization
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Solution Overview
Problem
Existing high electron mobility transistors (HEMTs) face challenges in enhancing conducting current due to increased Coulomb scattering and process uniformity issues, which degrade electron mobility and limit current enhancement.
Innovation Solution
Incorporating an N-type doped III-V semiconductor enhancement layer between the gate and drain electrodes, deepening the quantum well to increase two-dimensional electron gas concentration and improve conducting current, while also allowing for the formation of both depletion and enhancement mode transistors with reduced circuit complexity and production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If material concentration is fine-tuned and spacer structures are added to enhance two-dimensional electron gas concentration, then the two-dimensional electron gas is enhanced by band-structure modulation, but Coulomb scattering is also enhanced which degrades electron mobility and the net current may not increase
Solution Approach 1:
The patent applies local quality by creating a spatially non-uniform doping profile in the barrier layer. Specifically, the barrier layer has a first doping concentration in a first region and a second doping concentration in a second region, with the second doping concentration being higher than the first. This localized variation in doping concentration allows enhancement of electron mobility in specific regions without uniformly increasing Coulomb scattering throughout the entire structure, thereby resolving the contradiction between enhancing electron gas concentration and maintaining electron mobility.
2Quantity of substance
If material concentration is fine-tuned and spacer structures are added to enhance two-dimensional electron gas concentration, then band-structure modulation occurs, but process uniformity control becomes a great challenge
Solution Approach 1:
The patent employs parameter changes by varying the doping concentration parameter within the barrier layer. The barrier layer transitions from a uniform doping structure to a graded or multi-region doping structure where the doping concentration parameter changes spatially. This approach allows achieving enhanced two-dimensional electron gas concentration through controlled parameter variation rather than through complex spacer structures, thereby improving process uniformity control while still achieving the desired electronic properties.
3Reliability
If existing high electron mobility transistor structures are used, then the transistors are adequate for their intended purposes, but the conducting current needs to be improved
Solution Approach 1:
The patent utilizes composite materials by combining the barrier layer with different doping concentrations in different regions, integrated with the channel layer and source/drain structures. This composite structure allows the transistor to maintain its fundamental functionality while achieving enhanced conducting current through the optimized doping profile in the barrier layer, which creates favorable band alignment and reduces scattering mechanisms without compromising device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances conducting current by increasing two-dimensional electron gas concentration and allows for the creation of both depletion and enhancement mode transistors, offering improved performance and reduced standby power dissipation with lower production costs.
Implementation Method 1
deepening the quantum well to increase two-dimensional electron gas concentration
Implementation Method 2
The two-dimensional electron gas is enhanced by band-structure modulation
Implementation Method 3
Coulomb scattering is also enhanced by the above method, and this can degrade electron mobility
Data Source
AI summary
A high electron mobility transistor includes a buffer layer disposed on a substrate. A barrier layer is disposed on the buffer layer. A channel layer is disposed in the buffer layer and is adjacent to the interface between the buffer layer and the barrier layer. A gate electrode is disposed on the barrier layer. A drain electrode is disposed on the barrier layer on a first side of the gate electrode. A source electrode is disposed on the barrier layer on a second side of the gate electrode. A first enhancement layer is disposed on the barrier layer and the channel layer between the gate electrode and the drain electrode and is not in direct contact with the gate electrode, the source electrode, or the drain electrode. The first enhancement layer is an N-type doped III-V semiconductor.