HEMT Protective Structure for ESD Without Slower Gate Switching

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Solution Overview

Problem

III-V high electron mobility transistors (HEMTs) are susceptible to electrostatic discharge (ESD) strikes due to their lower threshold and breakdown voltages, and conventional ESD protection methods using resistors in series result in slower gate transition speeds during non-ESD events.

Innovation Solution

A protective structure integrating depletion-mode and enhancement-mode transistors, where the depletion-mode transistor has a gate coupled to ground and a source/drain terminal coupled to an integrated circuit component, and the enhancement-mode transistor has a gate coupled to the source/drain terminal of the depletion-mode transistor, forming a heterojunction with AlGaN/GaN layers, to enable current flow and voltage biasing, thereby providing ESD protection without adding resistors in series.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a resistor is added in series with ESD protective elements, then ESD protection capability is improved, but gate transition speed deteriorates

Engineering Contradiction:

ImproveESD protection capabilityVSAvoidgate transition speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The protective structure is segmented into two distinct transistor types: a depletion-mode transistor for ESD protection and an enhancement-mode transistor for normal operation. This segmentation allows each transistor to be optimized for its specific function, with the depletion-mode transistor providing ESD protection without affecting the speed of the enhancement-mode transistor during normal operation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The depletion-mode transistor acts as an intermediary element between the ESD strike and the enhancement-mode transistor. It provides a dedicated ESD current path that bypasses the enhancement-mode transistor, preventing ESD damage while avoiding the speed penalty of adding resistance in series with the main signal path.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If conventional ESD protection methods are used, then device protection is improved, but operational performance deteriorates

Engineering Contradiction:

Improvedevice protectionVSAvoidoperational performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The protective structure applies different characteristics to different parts of the circuit: the depletion-mode transistor is specifically designed with ESD protection characteristics (higher breakdown voltage, different threshold) and is placed only in the ESD protection path, while the enhancement-mode transistor maintains optimal performance characteristics for normal operation. This local differentiation allows ESD protection without compromising overall operational performance.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20240063301A1Protective structure with depletion-mode and enhancement-mode transistors

Publication Date: 2024.02.22 GLOBALFOUNDRIES US INC

AI summary

Disclosed are protective structures using depletion-mode and enhancement-mode transistors. A structure according to the disclosure may include a depletion-mode transistor having a gate coupled to ground and a first source/drain terminal. An enhancement-mode transistor includes a gate coupled to a second source/drain terminal of the depletion-mode transistor and a first source/drain terminal coupled to the gate of the depletion-mode transistor. The depletion-mode transistor limits a current flow from the first source/drain terminal to the gate of the enhancement-mode transistor.