HEMT Source Field Plate Layout for Lower Gate Parasitic Capacitance

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Solution Overview

Problem

Current high electron mobility transistor (HEMT) devices experience power loss and reduced speed due to parasitic capacitance generated between the source field plate and the gate electrode.

Innovation Solution

The HEMT device design includes a source field plate with specific configurations, such as non-overlapping top-view patterns and strategically positioned openings, to reduce the overlapping area with the gate electrode, thereby minimizing parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a source field plate is used to adjust the electric field, then the electrical performance of the device is improved, but parasitic capacitance is generated between the source field plate and the gate electrode, resulting in power loss and reduced device speed

Engineering Contradiction:

Improveelectrical performanceVSAvoidpower loss

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The source field plate is segmented into multiple portions (first field plate portion, second field plate portion, third field plate portion) with different configurations. The first and second field plate portions are positioned to avoid overlapping with the gate electrode, while the third field plate portion connects them. This segmentation allows the field plate to maintain its electric field adjustment function while reducing parasitic capacitance by minimizing overlap area with the gate electrode.

Inventive Principle:

Principle #1Segmentation

2Reliability

Engineering Contradiction:

Improveelectrical performanceVSAvoiddevice speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The source field plate is divided into multiple portions with the first and second field plate portions positioned to minimize overlapping with the gate electrode. This segmentation reduces the parasitic capacitance between the field plate and gate electrode, thereby reducing the capacitive loading effect and improving the device switching speed while maintaining electrical performance.

Inventive Principle:

Principle #1Segmentation

3Reliability

If the source field plate overlaps with the gate electrode, then the electric field adjustment function is enhanced, but the overlapping area increases parasitic capacitance

Engineering Contradiction:

Improveelectric field adjustmentVSAvoidparasitic capacitance

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The source field plate is segmented into multiple portions positioned at different locations. The first field plate portion is connected to the source electrode and positioned on the first side of the gate electrode without overlapping it. The second field plate portion is positioned on the second side of the gate electrode without overlapping it. The third field plate portion connects the first and second portions. This segmentation maintains the electric field adjustment function while minimizing the overlapping area with the gate electrode, thereby reducing parasitic capacitance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the source field plate have different spatial relationships with the gate electrode. The first and second field plate portions are positioned to avoid overlapping with the gate electrode, while the third field plate portion serves as a connector. This local differentiation allows the field plate to perform its electric field adjustment function in critical areas while avoiding parasitic capacitance generation in areas where overlap would be harmful.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces parasitic capacitance, leading to decreased power loss and improved device speed.

Implementation Method 1

parasitic capacitance is generated between the source field plate and the gate electrode, resulting in power loss

Methodology Applied

Scientific EffectParasitic capacitance: Capacitance

Data Source

PatentUS12176403B2High electron mobility transistor device

Publication Date: 2024.12.24 UNITED MICROELECTRONICS CORP

AI summary

A high electron mobility transistor (HEMT) device including the following components is provided. A gate electrode is located on a barrier layer. A source electrode is located on the first side of the gate electrode. A drain electrode is located on the second side of the gate. A source field plate is connected to the source electrode. The source field plate includes first, second, and third field plate portions. The first field plate portion is connected to the source electrode and is located on the first side of the gate electrode. The second field plate portion is located on the second side of the gate electrode. The third field plate portion is connected to the end of the first field plate portion and the end of the second field plate portion. The source field plate has a first opening located directly above the gate electrode.