HEMT Field Plate Under Capping Layer for Power Efficiency

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Solution Overview

Problem

High-electron-mobility transistors (HEMTs) face challenges in achieving low breakdown voltages and high power efficiency due to high voltages in the junction between the channel and drift region, leading to increased resistance and reduced device speed.

Innovation Solution

The implementation of a field plate structure, where the field plate is disposed closer to the channel by being placed under the capping layer, reduces the electric field near the gate and lowers the gate-to-drain capacitance, enhancing power efficiency and device speed through the reduced surface field (RESURF) technique.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the field plate is disposed closer to the channel by being placed under the capping layer, then the electric field near the gate is reduced and gate-to-drain capacitance is lowered, but the device structure becomes more complex

Engineering Contradiction:
Improvepower efficiencyVSAvoidstructure complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The field plate is repositioned from a conventional location to underneath the capping layer, utilizing the vertical dimension beneath existing structures. This spatial reconfiguration allows the field plate to be closer to the channel without increasing lateral footprint, thereby reducing electric field and capacitance while avoiding proportional increases in overall device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The field plate is nested within the existing device structure by placing it under the capping layer. This nesting approach integrates the field plate into the vertical stack of the HEMT device, allowing it to function effectively while sharing space with other device components, thus improving power efficiency without linearly increasing device complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If high voltage is applied in the junction between the channel and drift region, then the breakdown voltage increases, but the resistance increases and device speed reduces

Engineering Contradiction:
Improvebreakdown voltageVSAvoiddevice speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The field plate is positioned to create a localized modification of the electric field distribution specifically in the critical region near the gate and channel junction. By concentrating the field modulation effect where it is most needed, the device achieves improved breakdown characteristics without introducing high voltage conditions that would slow down overall device operation.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The field plate acts as an intermediary structure between the gate and the drift region, mediating the electric field distribution in the junction area. It provides a controlled pathway for field management that allows high breakdown voltage to be achieved without the adverse effects of high voltage on resistance and device speed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration increases the figure of merit of power devices by reducing the electric field and capacitance, resulting in improved switching speed and power efficiency in HEMTs.

Implementation Method 1

reduces the electric field near the gate and lowers the gate-to-drain capacitance

Methodology Applied
Scientific EffectElectric Field: Electric Field

Implementation Method 2

enhancing power efficiency and device speed through the reduced surface field (RESURF) technique

Methodology Applied
Scientific EffectReduced Surface Field (RESURF) technique:

Data Source

PatentUS11011380B2High-electron-mobility transistor and manufacturing method thereof
Publication Date: 2021.05.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11011380B2 patent drawing
  • US11011380B2 patent drawing
  • US11011380B2 patent drawing

AI summary

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformably over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.