HEMT Field Plate Extension for Gate Leakage Suppression
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Solution Overview
Problem
Switch mode power amplifiers face challenges in achieving robust operation at high compression due to large forward currents from gate to source during microwave frequency operation, which is difficult to manage effectively.
Innovation Solution
A high electron mobility transistor (HEMT) with a gate dielectric to limit forward conduction and a gate field plate extension is used, along with three dielectric layers under the field plate to minimize gate capacitance impact, and etch selectivity between insulators is employed in fabricating the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate field plate extension is added to shape the peak electric field, then the operation robustness under high compression is improved, but the gate capacitance increases
Solution Approach 1:
A gate dielectric layer is introduced as an intermediary between the gate field plate extension and the underlying semiconductor structure. This dielectric layer enables the field-shaping function of the plate extension while electrically isolating it to prevent direct capacitance coupling, thus resolving the contradiction between improving operation robustness and minimizing gate capacitance increase.
2Use of energy by moving object
If three dielectric layers are used under the field plate to minimize gate capacitance impact, then the gate capacitance is reduced, but the device complexity increases
Solution Approach 1:
The dielectric structure under the field plate is segmented into three distinct layers with different materials and thicknesses. This segmentation allows each layer to serve a specific function: the first layer provides primary electrical isolation, the second layer optimizes electric field distribution, and the third layer minimizes capacitance coupling. This segmented approach achieves capacitance reduction while maintaining manageable device complexity through functional decomposition.
3Reliability
If a gate dielectric is added to limit forward conduction, then the gate leakage is suppressed, but the manufacturing complexity increases
Solution Approach 1:
The gate dielectric layer is merged with the existing multi-layer dielectric structure under the field plate, forming an integrated dielectric system. This merging approach allows the gate dielectric to be deposited and processed together with the other dielectric layers using the same fabrication equipment and process conditions, thereby achieving gate leakage suppression without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables more robust operation under high compression by suppressing gate leakage and shaping the peak electric field with minimal added gate capacitance, ensuring reliable performance in high-voltage, high-temperature conditions.
Implementation Method 1
a gate dielectric to limit forward conduction from gate to source under high input drive and suppress gate leakage during high-voltage, high-temperature operation
Implementation Method 2
a gate field plate extension is provided to shape the peak electric field
Implementation Method 3
Three dielectric layers are employed under the field plate and provide a thicker dielectric to minimize impact on gate capacitance
Data Source
Figure 1~2
Figure 3~4
AI summary
Disclosed are a switch mode power amplifier and a field effect transistor especially suitable for use in a switch mode power amplifier. The transistor is preferably a compound high electron mobility transistor (HEMT) having a source terminal and a drain terminal with a gate terminal therebetween and positioned on a dielectric material. A field plate extends from the gate terminal over at least two layers of dielectric material towards the drain. The dielectric layers preferably comprise silicon oxide and silicon nitride. A third layer of silicon oxide can be provided with the layer of silicon nitride being positioned between layers of silicon oxide. Etch selectivity is utilized in etching recesses for the gate terminal.