HEMT Field Plate Layout for Higher Breakdown With Fewer Masks
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Solution Overview
Problem
Conventional high electron mobility transistors (HEMTs) have complex process steps and high manufacturing costs due to the formation of field plates, which also limit the breakdown voltage.
Innovation Solution
The proposed solution involves simplifying the fabrication process of HEMTs by using fewer photo-masks and metal layers to form multiple field plates, thereby reducing costs and increasing the breakdown voltage through enhanced electric field redistribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional field plate formation processes are used, then breakdown voltage is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the formation of multiple field plates with the gate electrode into a single metal layer deposition step. The metal layer is deposited to cover the entire region including gate electrode areas and field plate areas, then patterned in one step to create both structures. This merging of formation processes reduces the number of separate fabrication steps while maintaining the breakdown voltage enhancement provided by multiple field plates.
Solution Approach 2:
The patent uses a single metal layer that serves dual purposes: forming both the gate electrode and multiple field plates. This multi-functional approach allows one metal layer to perform what traditionally required separate metal layers and processes, thereby simplifying the overall device structure and fabrication process while still achieving the electrical field distribution benefits of multiple field plates.
2Reliability
If conventional field plate formation processes are used, then breakdown voltage is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines the formation of multiple field plates with the gate electrode into a single metal layer deposition step. The metal layer is deposited to cover the entire region including gate electrode areas and field plate areas, then patterned in one step to create both structures. This merging of formation processes reduces the number of separate fabrication steps while maintaining the breakdown voltage enhancement provided by multiple field plates.
Solution Approach 2:
The patent uses a single metal layer that serves dual purposes: forming both the gate electrode and multiple field plates. This multi-functional approach allows one metal layer to perform what traditionally required separate metal layers and processes, thereby simplifying the overall device structure and fabrication process while still achieving the electrical field distribution benefits of multiple field plates.
3Device complexity
If fewer photo-masks and metal layers are used, then device complexity is reduced, but electric field redistribution capability decreases
Solution Approach 1:
The patent segments the single metal layer into multiple functional regions during the patterning step. The metal layer is patterned to create distinct gate electrode regions and multiple field plate regions within the same layer. This segmentation allows the single metal layer to provide multiple electric field redistribution zones, maintaining the reliability benefits of multiple field plates while reducing the number of metal layers required.
Solution Approach 2:
The patent transitions from a vertical stacking approach (multiple metal layers) to a lateral distribution approach (multiple field plates in the same layer). By arranging multiple field plates side-by-side in the same metal layer rather than stacking them in separate layers, the patent achieves electric field redistribution across multiple zones without increasing the number of metal layers, thus resolving the contradiction between device complexity and field redistribution capability.
Data Source
AI summary
A high electron mobility transistor includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate in sequence. A source electrode and a drain electrode are disposed on the semiconductor channel layer. A semiconductor cap layer is disposed on the semiconductor barrier layer. A first dielectric layer is disposed over the source electrode, the semiconductor cap layer and the drain electrode. A first via passes through the first dielectric layer and is extended downward onto the semiconductor cap layer. A gate electrode is disposed on the first dielectric layer and in contact with the first via. A first field plate is disposed in the first dielectric layer. A second field plate is disposed on the first dielectric layer and in contact with the first field plate.