HEMT Gate Air Gap Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing high electron mobility transistors (HEMTs) face issues such as decreased current gain cut-off frequency due to unfavorable gate parasitic capacitances and threshold voltage instability caused by dielectric charge traps, limiting their high frequency performance.
Innovation Solution
A high electron mobility transistor (HEMT) is developed with an air gap formed by selectively removing an insulating layer and/or a spacer between the gate structure and the passivation layer through a selective wet etching process, reducing parasitic capacitances and gate leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional HEMT structure with continuous dielectric layer is used, then the device structure is simple and easy to manufacture, but gate parasitic capacitances increase and high frequency performance deteriorates
Solution Approach 1:
The continuous dielectric layer is segmented by removing portions to form air gaps between the gate structure and passivation layer. This segmentation reduces the parasitic capacitance area while maintaining structural integrity, directly improving high frequency performance without requiring complete redesign of the device architecture.
Solution Approach 2:
Air gaps are introduced at specific locations (gate edges and selected regions) rather than uniformly throughout the structure. This local modification optimizes the electric field distribution and reduces parasitic capacitance precisely where it most impacts high frequency performance, while keeping other regions intact for manufacturing simplicity.
2Reliability
If dielectric material is used to cover the gate structure, then the manufacturing process is simple, but dielectric charge traps cause threshold voltage instability
Solution Approach 1:
Dielectric material is removed from critical regions adjacent to the gate structure where charge traps would most adversely affect threshold voltage stability. By extracting the problematic dielectric material and replacing it with air gaps, the source of charge trap-induced instability is eliminated while maintaining the overall manufacturing process simplicity.
3Reliability
If the gate structure is closely covered by passivation layer, then the device structure is compact, but parasitic transistor near gate edge causes gate leakage current
Solution Approach 1:
Air gaps serve as intermediary regions between the gate structure and passivation layer, electrically isolating the gate edge from the passivation layer. This intermediary air region prevents the formation of parasitic transistors at the gate edge, reducing gate leakage current while maintaining a compact overall device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of an air gap in the HEMT reduces gate parasitic capacitances and dielectric charge traps, leading to improved high frequency performance and increased current gain cut-off frequency.
Implementation Method 1
forming an air gap formed by selectively removing an insulating layer and/or a spacer between the gate structure and the passivation layer of the HEMT through a selective wet etching process
Data Source
AI summary
A method for forming a high electron mobility transistor includes the steps of forming an epitaxial stack on a substrate; forming a gate structure on the epitaxial stack, wherein the gate structure comprises a semiconductor gate layer, a metal gate layer on the semiconductor gate layer, and a spacer on a top surface of the semiconductor gate layer and a sidewall of the metal gate layer; forming a passivation layer covering the epitaxial stack and the gate structure; forming an opening through the passivation layer on the gate structure to expose a portion of the spacer; and removing the spacer through the opening to form an air gap between the sidewall of metal gate layer, the top surface of the semiconductor gate layer and a sidewall of the passivation layer.