HEMT Gate-Source Bus Layout for Reduced Gate Oscillation
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Solution Overview
Problem
GaN power devices used in fast-switching applications experience significant gate oscillations due to resonance phenomena, which can lead to device malfunction or destruction if not properly managed, as existing topologies for gate signal distribution do not adequately mitigate these oscillations.
Innovation Solution
A High Electron Mobility Transistor (HEMT) power device design with a specific metallization topology that includes a gate bus and source bus arrangement, where the source bus electrically shields the gate bus, canceling out inductive parasitic components and decoupling the control signal from the drain potential, thereby reducing unwanted oscillations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate signal distribution topologies are used, then device simplicity is maintained, but gate oscillations occur due to resonance phenomena between gate signal path inductance and device substrate capacitance
Solution Approach 1:
The patent introduces an intermediary source bus that acts as a shield between the gate bus and the substrate. This source bus is positioned to electrically shield the gate bus, thereby mitigating the resonance phenomena and oscillations without requiring fundamental changes to the overall device architecture.
Solution Approach 2:
The patent adds a spatial dimension to the solution by positioning the source bus in a specific three-dimensional arrangement relative to the gate bus and substrate. The source bus is placed above the substrate and configured to shield the gate bus, utilizing vertical spacing and horizontal positioning to create effective electromagnetic shielding.
2Reliability
If gate signal path parasitic components are reduced to minimize oscillations, then gate oscillation is reduced, but the device becomes more sensitive to voltage peaks from Miller effect
Solution Approach 1:
The patent implements beforehand cushioning by pre-positioning the source bus as a shield before oscillations can develop. This proactive shielding structure is designed in advance to intercept and mitigate electromagnetic interference and voltage peaks before they can affect the gate terminal, providing protective cushioning against harmful factors.
3Speed
If fast-switching operation is implemented to improve power device performance, then switching speed increases, but gate oscillations are exacerbated due to high voltage and current gradients
Solution Approach 1:
The patent applies preliminary anti-action by introducing the source bus shield that preemptively counteracts the resonance phenomena and oscillations caused by fast-switching operations. The shielding structure is designed to oppose and cancel out the harmful electromagnetic effects that arise during high-speed switching, allowing fast-switching performance to be maintained without gate signal instability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described HEMT power device effectively minimizes gate oscillations during switching phases, reducing the risk of damage to the gate region and ensuring stable operation by balancing the conductive paths and canceling out inductive parasitic components in the control signal.
Implementation Method 1
the source bus electrically shields the gate bus, canceling out inductive parasitic components
Implementation Method 2
a semiconductive heterostructure (generally based on AlGaN/GaN layers and therefore the device is also referred to as 'GaN power device') allows a so-called two-dimensional electron gas (2DEG) to be generated spontaneously in the device
Implementation Method 3
The spontaneous channel may be modulated, in use, by applying suitable voltages to a gate region (commonly referred to as 'gate') of the device
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A heterojunction power device (1) includes: a substrate (21) containing semiconductor material; a first active area (20a) and a second active area (20b), arranged on the substrate (21) symmetrically opposite with respect to an axis of symmetry (H) and accommodating respective heterostructures (25, 27, 29); a separation region (23), extending along the axis of symmetry (H) between the first active area (20a) and the second active area (20b). The power device (1) further comprises: a gate conductive bus (35) configured to distribute a first electric potential (VG) of the power device (1) in parallel to the first and the second active areas (20a, 20b); a source conductive bus (55) configured to distribute a second electric potential (VS) of the power device (1), different from the first electric potential (VG), in parallel to the first and the second active areas (20a, 20b). The gate conductive bus (35) and the source conductive bus (55) extend along the axis of symmetry (H) above the separation region (23) and the source conductive bus (55) overlies the gate conductive bus (35).