HEMT Gate Clamp Circuit for False Turn-On Suppression

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Solution Overview

Problem

High Electron Mobility Transistors (HEMTs) with low gate threshold values experience false turn-on due to sudden voltage surges between the drain and source, leading to short circuits, especially when parasitic capacitance is small and voltage change rate is high, causing damage.

Innovation Solution

A semiconductor device configuration with a first transistor and a second transistor, where the first gate electrode and second drain electrode are electrically connected, and the first source electrode and second source electrode are not, allowing the second transistor to clamp the gate-source voltage fluctuation and set a negative reference potential, preventing the voltage from exceeding the gate threshold.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If HEMT is used with low gate threshold value (2V or less), then switching performance is improved, but false turn-on occurs due to voltage surge between drain and source

Engineering Contradiction:
Improveswitching speedVSAvoidfalse turn-on prevention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

A second transistor is introduced as an intermediary component between the gate and source of the first transistor. This second transistor acts as a mediator to clamp the gate-source voltage, preventing voltage surges from causing false turn-on while allowing the first transistor to maintain its low threshold value for fast switching performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate-source voltage parameter is actively controlled by the second transistor, which changes the voltage level dynamically. By clamping the gate-source voltage to remain below the threshold, the system maintains reliable operation while the first transistor retains its fast switching characteristics through the low threshold value.

Inventive Principle:
Principle #35Parameter changes

2Speed

If parasitic capacitance is made small to improve switching response, then voltage change rate increases, but surge voltage occurs due to parasitic inductance

Engineering Contradiction:
Improvevoltage change rateVSAvoidsurge voltage
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The second transistor converts the harmful surge voltage effect into a beneficial voltage clamping mechanism. By detecting and actively limiting the gate-source voltage, the harmful inductive kickback is transformed into a controlled voltage regulation function that protects the transistor while allowing fast switching.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If FET is added for clamping between gate and source, then gate-source voltage fluctuation is suppressed, but voltage is regulated only to 0V which is insufficient when gate threshold is not high enough

Engineering Contradiction:
Improvevoltage fluctuation suppressionVSAvoidvoltage reference flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

Instead of regulating the gate-source voltage to 0V (conventional approach), the invention inverts the reference by using the second transistor's source electrode as a movable reference potential. This allows the gate-source voltage to be clamped at a negative reference value, providing sufficient margin below the threshold voltage for reliable operation.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS12148683B2Semiconductor device
Publication Date: 2024.11.19 ROHM CO LTD
  • US12148683B2 patent drawing
  • US12148683B2 patent drawing
  • US12148683B2 patent drawing

AI summary

A semiconductor device includes: a first transistor provided with an electron transit layer made of a nitride semiconductor, a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor that includes a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode and the second drain electrode are electrically connected to each other, while the first source electrode and the second source electrode are not electrically connected to each other.