HEMT Gate Electrode Structure With Crystallinity Control Film
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Solution Overview
Problem
Existing semiconductor devices face high electrical resistance in the gate electrode, leading to signal loss and deterioration of high-frequency gain.
Innovation Solution
A semiconductor device design that includes a gate electrode with a crystallinity control film and multiple metal films, where the first metal film is formed on the crystallinity control film, improving its crystallinity and that of the second metal film, thereby reducing the electrical resistance of the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate electrode structure is used, then the device structure is simple, but the electrical resistance of the gate electrode is high
Solution Approach 1:
The gate electrode is divided into multiple functional layers: a crystallinity control film layer and multiple metal film layers (including low-resistance metal and reflective metal). This segmentation allows each layer to perform its specific function - the crystallinity control film improves crystal orientation, while the metal layers provide electrical conductivity and signal reflection, collectively reducing electrical resistance without requiring a single complex material
Solution Approach 2:
The gate electrode uses a composite structure combining different materials with complementary properties. The crystallinity control film (e.g., GaN, AlN, or ZnO) provides crystal orientation control, while the metal films (e.g., Al, Mo, W) provide electrical conductivity and reflectivity. This composite approach reduces electrical resistance by leveraging the strengths of each material rather than relying on a single material
2Reliability
If the gate electrode resistance is high, then the device structure is simple, but signal loss increases and high-frequency gain deteriorates
Solution Approach 1:
The gate electrode is segmented into functional layers where the crystallinity control film improves crystal orientation for better electrical properties, the low-resistance metal layer minimizes conduction losses, and the reflective metal layer enhances high-frequency signal performance. This segmentation addresses signal loss and gain deterioration through coordinated layer functions
Solution Approach 2:
The invention changes the electrical parameters of the gate electrode by introducing a crystallinity control film that improves crystal orientation and reduces resistance. This parameter change (from high resistance to low resistance) directly reduces signal loss and improves high-frequency gain without requiring complete structural redesign
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces electrical resistance, minimizing signal loss and improving the characteristics and reliability of the semiconductor device by enhancing the crystallinity of the metal films.
Implementation Method 1
a first metal film disposed on the crystallinity control film and in Schottky contact with the semiconductor layer via the inner walls, extending to each other, of the second opening and the first opening
Data Source
AI summary
A semiconductor device includes a substrate, a semiconductor layer disposed on the substrate, an insulating layer disposed on the semiconductor layer and having a first opening formed therein, a gate electrode disposed on the insulating layer and in contact with the semiconductor layer via the first opening, and a source electrode and a drain electrode in ohmic contact with the semiconductor layer. The gate electrode includes a crystallinity control film disposed on the insulating layer and having a second opening formed such that an inner wall thereof extends to an inner wall of the first opening toward the substrate in plan view in a direction perpendicular to a top surface of the substrate, and a first metal film disposed on the crystallinity control film and in Schottky contact with the semiconductor layer via the inner walls, extending to each other, of the second opening and the first opening.


