HEMT Gate Structure With Dielectric Block for Lower Parasitic Capacitance
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Solution Overview
Problem
The short channel effect in nitride-based high electron mobility transistors due to parasitic capacitance and fringing capacitance hinders the improvement of frequency characteristics, and existing manufacturing techniques struggle to effectively reduce these capacitances.
Innovation Solution
A high electron mobility transistor design incorporating a dielectric block surrounding the gate electrode, cavity filters, and a T-shaped gate structure to minimize parasitic and fringing capacitances, along with a manufacturing method that includes forming semiconductor layers, electrodes, and protection films using processes like MBE and PECVD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate length is shortened to increase frequency characteristics, then the cutoff frequency is improved, but the parasitic capacitance and fringing capacitance become dominant and deteriorate the frequency characteristics
Solution Approach 1:
The patent extracts and removes the harmful parasitic capacitance by introducing a dielectric block that physically separates the gate electrode from the semiconductor layer, eliminating the capacitive coupling that causes fringing capacitance
Solution Approach 2:
The dielectric block acts as an intermediary element between the gate electrode and the semiconductor layer, preventing direct capacitive interaction while maintaining the electrical functionality of the transistor
2Object-generated harmful factors
If the upper part of the gate electrode is spaced apart from the semiconductor layer to reduce parasitic capacitance, then the frequency characteristics improve, but the structural stability deteriorates due to the narrow lower part supporting the wide upper part
Solution Approach 1:
The patent resolves the structural stability issue by extending the gate electrode in the vertical dimension rather than horizontally, creating a T-shaped structure where the gate electrode rises vertically from the semiconductor layer surface, thus achieving capacitance reduction without compromising horizontal structural support
Solution Approach 2:
The gate electrode is segmented into distinct portions: a lower part that maintains structural support on the semiconductor layer and an upper part that extends vertically to reduce parasitic capacitance, with the dielectric block providing additional segmentation and separation
3Speed
If the area of the upper part of the gate electrode is increased to increase maximum resonance frequency, then the gate resistance is reduced, but the parasitic capacitance between the upper gate and semiconductor layer increases
Solution Approach 1:
The patent enables the upper gate electrode to have a larger area by extending it vertically in the third dimension, away from the semiconductor layer plane, thus increasing the conductive area for lower resistance and higher resonance frequency without increasing the planar area that would create parasitic capacitance
Data Source
AI summary
Provided is a high electron mobility transistor and a manufacturing method of the same. The high electron mobility transistor includes a semiconductor layer on a substrate, a source electrode and a drain electrode on both sides of the semiconductor layer, a gate electrode provided on the semiconductor layer between the source electrode and the drain electrode, and a dielectric block surrounding a bottom of the gate electrode.