Monolithic Gate Driver Integration for HEMT Voltage Spike Control

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Solution Overview

Problem

High-inductance between the driver and gate of power transistors in buck converters leads to uncontrolled gate voltage spikes, reducing efficiency and making it difficult to use HEMTs in power converters due to their susceptibility to these spikes.

Innovation Solution

Monolithic integration of part of the gate driver with the power HEMT on the same die, reducing parasitic resistance and inductance and eliminating voltage spikes, while allowing for efficient control of the gate voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the driver and power transistors are placed on separate dies, then the packaging is simpler and manufacturing is easier, but the parasitic inductance between driver and gate increases causing voltage spikes

Engineering Contradiction:
Improvepackaging simplicityVSAvoidgate voltage spikes
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent merges the gate driver and power transistor onto the same die, eliminating the need for inter-die connections and thereby removing the parasitic inductance that causes voltage spikes during switching transitions

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If dead time is increased to avoid cross-conduction, then reliability improves, but switching efficiency decreases

Engineering Contradiction:
Improvecross-conduction preventionVSAvoidswitching losses
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

By integrating the gate driver directly with the power transistor on the same die, the patent eliminates parasitic inductance, enabling precise control of gate voltage during switching transitions. This allows the use of minimal or zero dead time while preventing cross-conduction, thereby maintaining high switching efficiency

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If switching speed is increased to improve efficiency, then productivity improves, but gate voltage control becomes uncontrolled due to parasitic effects

Engineering Contradiction:
Improveswitching frequencyVSAvoidgate voltage control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The integration of gate driver and power transistor on the same die eliminates parasitic inductance, enabling precise and controlled gate voltage even at high switching frequencies, thus allowing fast switching without loss of control

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10438945B2Method of manufacturing a semiconductor die
Publication Date: 2019.10.08 INFINEON TECH AUSTRIA AG
  • US10438945B2 patent drawing
  • US10438945B2 patent drawing
  • US10438945B2 patent drawing

AI summary

A method of manufacturing a semiconductor die includes: forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a gate, a source and a drain; monolithically integrating a first gate driver HEMT with the power HEMT in the III-nitride semiconductor substrate, the first gate driver HEMT having a gate, a source and a drain and logically forming part of a driver; and electrically connecting the first gate driver HEMT to the gate of the power HEMT so that the first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device.