Gate Electrode Profile for HEMT Gap Elimination

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Solution Overview

Problem

Conventional methods of gate electrode formation in High Electron Mobility Transistors (HEMTs) lead to gaps between the gate electrode and the semiconductor surface, causing current collapse and increased capacitance, which negatively impact device performance.

Innovation Solution

A method involving the formation of a protective layer with an opening for the gate electrode, where the gate electrode extends on opposing sidewalls and has additional portions beyond the opening, reducing gaps and capacitance by using a second layer with a lower dielectric index to create a self-aligned stair-step profile.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional methods of gate electrode formation are used (depositing dielectric, etching through dielectric, depositing T-shaped gate electrode), then the gate electrode can be formed in the dielectric opening, but gaps are formed between the edges of the dielectric and the gate electrode due to isotropy of the dielectric etch

Engineering Contradiction:

Improvegate electrode formation processVSAvoidgap formation between dielectric and gate electrode

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent performs preliminary actions by forming the gate electrode to extend laterally on the dielectric surface before completing the dielectric deposition. This preliminary positioning ensures that when the dielectric is subsequently deposited to fill the opening, the gate electrode is already in place to prevent gap formation, thereby solving the manufacturing precision issue while maintaining ease of manufacture

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent transitions from a conventional planar gate electrode configuration to a three-dimensional configuration where the gate electrode extends laterally on the dielectric surface and vertically through the dielectric opening. This dimensional change allows the gate electrode to contact the semiconductor surface directly while being supported by the dielectric, eliminating gaps without compromising the manufacturing process

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If gaps are formed between the dielectric and gate electrode, then the gate electrode can be deposited, but unpassivated semiconductor surface is exposed causing current collapse and drift in the device

Engineering Contradiction:

Improvegate electrode depositionVSAvoiddevice operation stability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent converts the potential harm of gap formation into a benefit by designing the gate electrode to extend laterally on the dielectric surface. This configuration ensures that the gate electrode directly contacts the semiconductor surface while the dielectric provides support and insulation, eliminating unpassivated surfaces and preventing current collapse, thereby improving device reliability without complicating the deposition process

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Ease of manufacture

If a passivation layer is formed in the gap after formation of the gate, then the gap can be filled, but the passivation properties are inferior to that of the initial pre-gate dielectric

Engineering Contradiction:

Improvepost-gate passivation layer formationVSAvoidpassivation quality

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent performs preliminary dielectric deposition before gate electrode formation, allowing the dielectric to be formed at relatively high temperatures that provide superior passivation properties. By inverting the conventional sequence and forming the gate electrode to extend on the dielectric surface first, then completing the dielectric deposition, the patent ensures high-quality passivation is achieved before the gate is formed, eliminating the need for inferior post-gate passivation layers

Inventive Principle:

Principle #10Preliminary action

4Manufacturing precision

If the gate electrode completely fills the etched portion of the dielectric (dielectrically-supported T-gate or gamma gate), then gaps are prevented, but gate-drain capacitance and gate-source capacitance are increased

Engineering Contradiction:

Improvegap elimination between dielectric and gate electrodeVSAvoidgate capacitance

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by configuring the gate electrode to extend laterally on the dielectric surface in specific regions while maintaining appropriate spacing in other regions. This localized extension allows the gate electrode to contact the semiconductor surface and prevent gaps without excessively increasing the gate area, thereby eliminating gaps while controlling gate capacitance and avoiding excessive device complexity

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS7592211B2Methods of fabricating transistors including supported gate electrodes

Publication Date: 2009.09.22 WOLFSPEED INC

AI summary

Transistors are fabricated by forming a protective layer having an opening extending therethrough on a substrate, and forming a gate electrode in the opening. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion. Related devices and fabrication methods are also discussed.