HEMT Gate-Field Plate Layout for Lower Gate-Source Capacitance
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Solution Overview
Problem
Existing high electron mobility transistors (HEMTs) face challenges in reducing gate-to-source capacitance and require complex processing steps for separate field plate metal deposition.
Innovation Solution
The proposed solution involves forming a HEMT with a gate metal and a field plate made from the same material, with an airgap between them, which reduces gate-to-source capacitance and eliminates the need for separate metal deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate field plate metal deposition is used, then device performance can be optimized, but manufacturing process complexity increases
Solution Approach 1:
The patent combines the gate metal and field plate metal into a single continuous metal layer, eliminating the need for separate deposition processes. This merging approach maintains the electrical and functional performance benefits of having both gate and field plate structures while significantly simplifying the manufacturing process by reducing the number of deposition, patterning, and etching steps required.
Solution Approach 2:
The single metal layer serves dual functions as both the gate metal and field plate metal. By designing the metal layer with appropriate patterns and connections, it simultaneously provides the gate control function and the field plate function for reducing gate-to-source capacitance, eliminating the need for separate specialized metal layers.
2Manufacturing precision
If multiple metal deposition processes are used, then precise control over metal layers is achieved, but manufacturing time and cost increase
Solution Approach 1:
The patent consolidates multiple metal deposition processes into a single deposition step where one continuous metal layer is formed to serve as both gate metal and field plate metal. This approach maintains sufficient manufacturing precision for defining gate and field plate regions through patternning and connection design, while dramatically improving manufacturing efficiency by eliminating redundant deposition cycles.
3Speed
If gate-to-source capacitance is reduced, then switching speed improves, but device design complexity increases
Solution Approach 1:
The patent extracts the field plate function from a separate metal layer and integrates it into the gate metal layer itself. By creating an airgap between portions of the same metal layer, the design achieves reduced gate-to-source capacitance through the field plate effect while avoiding the added complexity of managing multiple metal layers, interfaces, and associated processing steps.
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to high electron mobility transistors and methods of manufacture. The structure includes: a semiconductor substrate; a gate structure on the semiconductor substrate; a gate metal connecting to the gate structure; and a field plate connected to a source region of the gate structure. The gate metal and the field plate include a same material.