HEMT Gate Structure with Interlayer for Normally-Off Operation

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Solution Overview

Problem

High electron mobility transistors (HEMTs) typically have a normally-on configuration, which limits their applicability due to the need for additional circuitry to turn them off, increasing cost and complexity, and existing methods to modify them to be normally-off can impact device parameters like leakage current and transconductance.

Innovation Solution

A gate structure for HEMTs is designed with a doped semiconductor region, an interlayer, and a gate electrode, where the doping concentration and interlayer thickness are optimized to ensure the channel is non-conductive at zero gate bias, controlling carrier injection, recombination, static threshold voltage, and dynamic threshold voltage shift to achieve a normally-off configuration without significantly affecting device parameters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a thick p-type doped GaN layer is formed under the gate electrode to deplete the inversion layer and shift the threshold voltage to positive values, then the HEMT achieves a normally-off configuration, but device parameters such as leakage current, maximum gate voltage, and transconductance are adversely impacted

Engineering Contradiction:
Improvenormally-off configurationVSAvoiddevice parameters (leakage current, maximum gate voltage, transconductance)
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

An interlayer is introduced between the doped semiconductor region and the gate electrode to act as an intermediary that blocks carrier injection into the channel while still allowing the electric field to penetrate and deplete the inversion layer. This mediator enables the normally-off function without the harmful side effects of direct carrier injection that occur with conventional thick doped layers.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The doping concentration of the doped semiconductor region is precisely controlled and optimized to achieve the desired depletion effect without excessive carrier injection. By adjusting this parameter, the gate structure can shift the threshold voltage to positive values while minimizing adverse impacts on leakage current and transconductance.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If the doping concentration of the doped semiconductor region is increased to ensure adequate depletion of the channel at zero gate bias, then the normally-off state is achieved, but carrier injection from the gate electrode to the channel increases, affecting dynamic threshold voltage shift

Engineering Contradiction:
Improvechannel depletion at zero gate biasVSAvoiddynamic threshold voltage shift
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The interlayer serves as a barrier that prevents direct carrier injection from the gate electrode into the channel during switching operations. This mediator allows the high doping concentration needed for adequate channel depletion while blocking the harmful carrier injection that would otherwise cause dynamic threshold voltage shifts and slow switching response.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate structure is segmented into distinct functional layers: the doped semiconductor region for creating the depletion field, the interlayer for blocking carrier injection, and the gate electrode for applying control voltage. This segmentation allows each layer to perform its specific function optimally without interfering with the others.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively transforms HEMTs into a normally-off state with improved dynamic switching behavior and reduced power consumption by balancing carrier injection and recombination, maintaining static performance and threshold voltage.

Implementation Method 1

The vertical field generated by a voltage applied to the gate electrode allows for on and off modulation of the inversion layer

Methodology Applied
Scientific EffectElectric field: Electric Field

Implementation Method 2

a portion of the channel adjacent the gate structure is non-conductive at zero gate bias

Methodology Applied
Scientific EffectDepletion:

Implementation Method 3

a rate of carrier injection from the gate electrode to the channel

Methodology Applied
Scientific EffectCarrier injection:

Implementation Method 4

a rate of recombination of injected carriers in the channel

Methodology Applied
Scientific EffectRecombination:

Implementation Method 5

a heterostructure body with buffer region, and a barrier region disposed on the buffer region and having a different band gap than the buffer region such that a two-dimensional charge carrier gas channel arises near an interface between the buffer region and the barrier region

Methodology Applied
Scientific EffectHeterojunction:

Implementation Method 6

a two-dimensional electron gas (2DEG) arises near the interface between the AlGaN barrier layer and the GaN buffer layer

Methodology Applied
Scientific EffectTwo-dimensional electron gas formation:

Data Source

PatentUS10038085B2High electron mobility transistor with carrier injection mitigation gate structure
Publication Date: 2018.07.31 INFINEON TECH AUSTRIA AG
  • US10038085B2 patent drawing
  • US10038085B2 patent drawing
  • US10038085B2 patent drawing

AI summary

A method includes providing a heterostructure body with a buffer region, and a barrier region disposed on the buffer region, and forming a gate structure for controlling the channel on the heterostructure body, the gate structure having a doped semiconductor region disposed on the heterostructure body, an interlayer disposed on the doped semiconductor region, and a gate electrode disposed on the interlayer. Forming the gate structure includes controlling a doping concentration of the doped semiconductor region such that a portion of the channel adjacent the gate structure is non-conductive at zero gate bias, and controlling electrical and geometrical characteristics of the interlayer based upon a relationship between the electrical and geometrical characteristics of the interlayer and corresponding effects on a static threshold voltage and a dynamic threshold voltage shift of the semiconductor device.