HEMT Gate Stack Structure for Lower Leakage and Etch Tolerance
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Solution Overview
Problem
Conventional high electron mobility transistors (HEMTs) face challenges in maintaining consistency in electrical performance due to difficulties in accurately controlling the lateral etching process for metal capping layers, leading to variations in width and increased gate leakage current.
Innovation Solution
A high electron mobility transistor design featuring a patterned semiconductor protection layer with resistivity between the semiconductor capping layer and interlayer dielectric layer, which prevents lateral etching and maintains the original electrical properties of the capping layer by acting as a buffer, reducing gate leakage current and ensuring consistency across devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a wet lateral etching process is used to fabricate the metal capping layer, then the metal capping layer can be formed, but the etching degree is difficult to accurately control, leading to variations in width and reduced consistency of electrical performances
Solution Approach 1:
A semiconductor protection layer with intermediate resistivity is introduced between the metal capping layer and the semiconductor capping layer. This protection layer acts as a mediator that prevents direct contact between the metal capping layer and semiconductor capping layer, thereby eliminating gate leakage current while maintaining ease of manufacture through standard deposition processes.
Solution Approach 2:
The patent changes the resistivity parameter of the protection layer to be higher than that of the metal capping layer, which fundamentally alters the electrical characteristics of the structure. This parameter change ensures that the protection layer blocks leakage current while allowing the manufacturing process to proceed with conventional techniques.
2Productivity
If the metal capping layer width varies due to uncontrolled etching, then individual HEMTs can be fabricated, but the consistency of electrical performances is reduced
Solution Approach 1:
The semiconductor protection layer serves as a buffer that decouples the dimensional variations of the metal capping layer from the electrical performance of the HEMT. By introducing this intermediate layer, the system can tolerate width variations without compromising electrical consistency, thus maintaining both productivity and reliability.
Solution Approach 2:
The protection layer is deposited beforehand to compensate for potential leakage issues. This pre-established protective barrier ensures that even if the metal capping layer has width variations, the electrical performance remains consistent because the protection layer prevents leakage pathways from forming.
3Device complexity
If the metal capping layer directly contacts the semiconductor capping layer, then the structure is simplified, but gate leakage current increases
Solution Approach 1:
The semiconductor protection layer is introduced as an intermediary between the metal capping layer and semiconductor capping layer. Although this adds a layer to the structure, it effectively blocks gate leakage current by utilizing its higher resistivity, thus resolving the contradiction between structural simplicity and electrical performance.
Solution Approach 2:
The patent employs a composite structure with multiple materials having different resistivity characteristics. The semiconductor protection layer, with its intermediate resistivity between the metal capping layer and semiconductor capping layer, creates a composite structure that prevents leakage while maintaining reasonable device complexity.
Data Source
AI summary
A high electron mobility transistor (HEMT) includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor capping layer, and a patterned semiconductor protection layer disposed on a substrate in sequence. The HEMT further includes an interlayer dielectric layer and a gate electrode. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.