Multi-Channel HEMT Gate Structure for Normally-Off Leakage Control
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Solution Overview
Problem
Existing high-electron-mobility transistors (HEMTs) face challenges in achieving a normally-off configuration and suffer from increased gate leakage current due to the doped semiconductor region, which affects power consumption and control characteristics.
Innovation Solution
The transistor device incorporates a gate structure with a region of doped type III-nitride semiconductor material surrounding the gate fin, combined with current blocking devices such as Schottky diodes and layers of type III-nitride semiconductor material along the sidewalls, to prevent carrier flow and mitigate gate leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a doped semiconductor region is used in the gate structure to achieve normally-off configuration, then the transistor can be turned off without gate bias, but gate leakage current increases
Solution Approach 1:
The gate structure is segmented into multiple functional regions: an undoped semiconductor region forming the gate fin, a doped semiconductor region extending into the gate trench to provide depletion, and current blocking devices (Schottky diodes) to prevent carrier flow. This segmentation allows each region to perform its specific function while mitigating the harmful effects of the doped region.
Solution Approach 2:
Current blocking devices (Schottky diodes) are introduced as intermediary elements between the doped semiconductor region and the two-dimensional charge carrier gas channels. These intermediaries prevent carriers from flowing between the doped region and the channels, thereby blocking the gate leakage current path while allowing the doped region to maintain its depletion function.
2Reliability
If multiple two-dimensional charge carrier gas channels are used to improve conduction, then electron mobility increases, but control complexity increases
Solution Approach 1:
The gate structure is designed with multi-functionality to control multiple channels simultaneously. The doped semiconductor region extends laterally to cover all gate trenches and vertically to reach multiple channel interfaces, providing universal control over all two-dimensional charge carrier gas channels through a single gate bias application, thereby simplifying the control mechanism despite the presence of multiple channels.
Solution Approach 2:
The gate structure utilizes vertical dimension by extending the doped semiconductor region from the gate trench surface down to the channel interfaces. This vertical extension allows the gate to control multiple channels at different depths within the semiconductor body, effectively managing multi-channel conduction through a three-dimensional gate structure rather than multiple separate gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved ON-OFF control and reduced gate leakage, resulting in enhanced performance and lower power consumption, particularly in multi-channel configurations.
Implementation Method 1
each of the two-dimensional charge carrier gas channels in the plurality being formed by a heterojunction between two regions of type III-nitride semiconductor material with different bandgaps
Implementation Method 2
a two-dimensional electron gas (2DEG) arises near the interface between the AlGaN barrier layer and the GaN channel layer
Implementation Method 3
a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches
Implementation Method 4
one or more current blocking devices that are configured to prevent carriers from flowing into or out of the region of doped type III-nitride semiconductor material
Data Source
AI summary
A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.