HEMT Gate Opening Process for Threshold Voltage and Yield
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Solution Overview
Problem
The existing methods for manufacturing high-electron-mobility transistors, such as atomic layer etching, are costly, time-consuming, and can result in surface damage to the barrier layer, leading to increased ON-resistance and reduced product yield due to over-etching and insufficient threshold voltage.
Innovation Solution
A method involving the formation of a protective layer on the semiconductor substrate, followed by an overlay layer, which allows for easy etching to create a gate opening and protects the barrier layer, enabling the p-type layer to be patterned before the source and drain are formed, thereby controlling threshold voltage and ON-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If atomic layer etching is used to pattern the p-type layer, then the transistor can be manufactured with proper threshold voltage, but the manufacturing cost increases and the process time is extended
Solution Approach 1:
A protective layer is formed on the barrier layer before patterning the p-type layer. This preliminary protective action allows subsequent etching processes to remove the p-type layer without damaging the underlying barrier layer, eliminating the need for costly and time-consuming atomic layer etching while ensuring proper threshold voltage control.
Solution Approach 2:
The protective layer acts as an intermediary between the etching process and the barrier layer. It enables the use of simpler, more efficient etching methods by absorbing the harmful effects of the etchant, thereby protecting the barrier layer and allowing faster manufacturing cycles.
2Reliability
If atomic layer etching is used to remove the p-type layer, then proper threshold voltage is achieved, but surface damage occurs on the barrier layer leading to reduced product yield
Solution Approach 1:
The protective layer is deposited beforehand to cushion and protect the barrier layer from damage during the p-type layer removal process. This prior protective measure prevents surface damage that would otherwise occur during etching, ensuring both proper threshold voltage and high product yield.
Solution Approach 2:
The protective layer serves as an intermediary shield between the aggressive etching chemicals and the sensitive barrier layer, allowing the etching process to proceed effectively while preventing damage to the underlying structure.
3Reliability
If the barrier layer is made thinner to increase threshold voltage, then the transistor performance improves, but the barrier layer becomes more susceptible to damage during processing
Solution Approach 1:
The protective layer is applied beforehand to cushion and protect the thinned barrier layer from damage during subsequent processing steps. This allows the barrier layer to be made thinner for higher threshold voltage without increasing susceptibility to processing damage.
Solution Approach 2:
The protective layer acts as an intermediary protective barrier that shields the vulnerable thinned barrier layer from harmful processing conditions, enabling the use of thinner barrier layers for improved transistor performance.
4Ease of manufacture
If the p-type layer is patterned after source and drain formation, then the manufacturing process follows conventional sequence, but special etching processes are required to prevent leakage and contamination
Solution Approach 1:
The protective layer is formed preliminarily before p-type layer patterning, enabling the use of simpler etching processes. This preliminary protective measure eliminates the need for complex special etching processes that would otherwise be required to prevent leakage and contamination during p-type layer removal.
Data Source
AI summary
A method for manufacturing a high-electron-mobility transistor includes the following steps: providing a semiconductor substrate, wherein the semiconductor substrate includes a channel layer and a barrier layer on the channel layer; forming a protective layer on the semiconductor substrate at a position corresponding to a gate opening; forming an overlay layer on the semiconductor substrate in an area around the protective layer, and removing the protective layer to form the gate opening; and forming a p-type layer in and at the gate opening and on the overlay layer. Compared with the prior art, the method for manufacturing a high-electron-mobility transistor lowers the technical threshold of manufacture, allows the threshold voltage (Vth) and ON-resistance (Rds(ON)) of each such transistor to be individually controlled at the desired levels, and can improve product yield effectively.