HEMT Gate PN Junction Formation for Lower Leakage Current
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Solution Overview
Problem
Current HEMT transistor manufacturing methods do not effectively improve the performance and reliability of high electron mobility transistors, particularly in defining a PN junction at the semiconductor gate interface to reduce leakage currents and enhance breakdown voltage.
Innovation Solution
A method involving a semiconductor gate layer with P-type dopant elements, compensated by oxygen atoms through an oxygen anneal to create a PN junction, followed by partial etching and additional oxygen compensation, resulting in a transistor structure with a PN junction at the gate interface and a peripheral N-type doped portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If P-type doping is applied to the semiconductor gate layer, then the breakdown voltage is increased, but leakage currents increase due to incomplete compensation of P-type dopant elements
Solution Approach 1:
The patent applies local quality by creating different doping regions within the gate layer: a first portion with compensated P-type doping (reducing leakage) and a second portion with uncompensated P-type doping (maintaining breakdown voltage). This spatial differentiation of doping compensation allows simultaneous optimization of both leakage current and breakdown voltage characteristics.
Solution Approach 2:
The gate layer is segmented into distinct functional portions: a first portion subjected to oxygen annealing for P-type doping compensation, and a second portion remaining P-type doped. This segmentation enables independent optimization of electrical properties in different regions, resolving the contradiction between leakage reduction and breakdown voltage enhancement.
2Object-generated harmful factors
If oxygen anneal is applied to compensate P-type doping, then leakage currents are reduced, but manufacturing complexity increases due to additional process steps
Solution Approach 1:
The patent applies partial action by performing oxygen annealing only on a first portion of the gate layer rather than the entire gate. This selective partial treatment reduces leakage currents in critical regions while avoiding unnecessary processing of other regions, thereby limiting the increase in manufacturing complexity to only where needed.
Solution Approach 2:
By applying oxygen annealing locally to specific portions of the gate layer rather than uniformly across the entire gate, the patent reduces leakage currents in critical areas while minimizing the impact on manufacturing process complexity. The localized treatment allows optimization where most needed without proportionally increasing overall process complexity.
3Manufacturing precision
If the gate layer is etched to remove excess material, then manufacturing precision is improved, but the structure becomes more complex requiring additional etching and compensation steps
Solution Approach 1:
The etching process is segmented into multiple sequential steps with intermediate oxygen annealing. The first etch removes excess gate material, followed by oxygen annealing to compensate P-type doping in the exposed region, then a second etch completes the shaping. This segmented approach achieves precise thickness control while managing the complexity through systematic multi-step processing.
Solution Approach 2:
The oxygen annealing step is performed as a preliminary action between etching steps to compensate P-type doping before final gate structure definition. This preliminary compensation prepares the material for subsequent precise etching, ensuring that the final gate structure has the desired electrical properties while achieving manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the transistor's performance by reducing leakage currents and increasing the avalanche voltage, thereby improving the overall reliability and efficiency of HEMT transistors for high-voltage applications.
Implementation Method 1
compensating for the P-type doping with oxygen atoms, in an upper portion of the semiconductor gate layer, by an oxygen anneal, so as to define a PN junction at the interface between the upper portion and a central portion of the semiconductor gate layer
Implementation Method 2
the gate comprises an upper portion and a central portion, the upper portion and the central portion comprising P-type dopant elements, and the upper portion comprising oxygen atoms compensating for the P-type doping
Data Source
AI summary
The present disclosure relates to a method of forming an HEMT transistor, comprising the following successive steps: a) providing a stack comprising a semiconductor channel layer, a semiconductor barrier layer on top of and in contact with the semiconductor channel layer, and a semiconductor gate layer arranged on top of and in contact with the semiconductor barrier layer, the semiconductor gate layer comprising P-type dopant elements; and b) compensating for the P-type doping with oxygen atoms, in an upper portion of the semiconductor gate layer, by an oxygen anneal, so as to define a PN junction at the interface between the upper portion and a central portion of the semiconductor gate layer.