HEMT Gate Structure With Protection Layer for Leakage Control

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Solution Overview

Problem

Conventional high electron mobility transistors (HEMTs) face challenges in maintaining consistent electrical performance due to difficulties in accurately controlling the lateral etching process for the metal capping layer, leading to variations in the width of the metal capping layers and reduced consistency in electrical performance.

Innovation Solution

A high electron mobility transistor design that includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor protection layer, a patterned semiconductor capping layer, an interlayer dielectric layer, and a gate electrode, where the patterned semiconductor protection layer is positioned between the gate electrode and the patterned semiconductor capping layer, with a resistivity between the capping layer and the interlayer dielectric layer, preventing unnecessary gate leakage current and maintaining the original electrical properties of the capping layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a wet lateral etching process is used to fabricate the metal capping layer, then the metal capping layer can be formed, but the etching degree is difficult to accurately control, leading to variations in the width of the metal capping layers

Engineering Contradiction:

Improvemetal capping layer formationVSAvoidwidth consistency of metal capping layer

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

A semiconductor protection layer with intermediate resistivity is introduced between the metal capping layer and the semiconductor capping layer. This protection layer acts as an intermediary that prevents direct contact between the gate electrode and the semiconductor capping layer, thereby eliminating the need for precise lateral etching control while maintaining proper electrical isolation.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The semiconductor protection layer is formed beforehand to establish a stable structural foundation before subsequent processing steps. This preliminary action ensures that the gate electrode has a defined interface with a controlled resistivity material, preventing width variations in the metal capping layer.

Inventive Principle:

Principle #10Preliminary action

2Ease of operation

If the gate electrode directly contacts the semiconductor capping layer, then electrical connection is achieved, but gate leakage current occurs due to point discharge on the side surfaces

Engineering Contradiction:

Improveelectrical connectionVSAvoidgate leakage current

Core Design Contradiction:

Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The semiconductor protection layer serves as an intermediary between the gate electrode and the semiconductor capping layer. It provides the necessary electrical connection while its higher resistivity prevents point discharge on side surfaces, thereby eliminating gate leakage current.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The resistivity parameter of the protection layer is specifically controlled to be higher than that of the metal capping layer. This parameter change prevents electrical breakdown and point discharge at the interface, eliminating gate leakage while maintaining proper electrical connection.

Inventive Principle:

Principle #35Parameter changes

3Ease of manufacture

If lateral etching is performed on the metal capping layer, then the structure is formed, but the original electrical properties of the capping layer are altered

Engineering Contradiction:

Improvestructure formationVSAvoidelectrical performance consistency

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The semiconductor protection layer acts as a protective intermediary that shields the semiconductor capping layer from etchant exposure. This allows structure formation through wet etching without altering the electrical properties of the capping layer, maintaining device reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The semiconductor protection layer is placed beforehand to cushion and protect the semiconductor capping layer during the wet etching process. This prior protection ensures that the capping layer's electrical properties remain unchanged while the necessary structural formation occurs.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12132103B2High electron mobility transistor and fabrication method thereof

Publication Date: 2024.10.29 VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION

AI summary

A high electron mobility transistor (HEMT) includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor capping layer, and a patterned semiconductor protection layer disposed on a substrate in sequence. The HEMT further includes an interlayer dielectric layer and a gate electrode. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.