HEMT Gate Layout With Side Contacts for Sub-THz Resistance Control

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Solution Overview

Problem

High electron mobility transistors (HEMTs) face challenges in reducing the adverse effect of electrical resistance on high-frequency signals, particularly in the sub-terahertz band, where manufacturing openings with large aspect ratios for the upper gate electrode is difficult due to small gate lengths and distances between source and drain electrodes.

Innovation Solution

A semiconductor device design featuring a gate electrode with a first region overlapping an active region and two second regions, where the metal film contacts the second regions, reducing the phase shift of high-frequency signals and allowing for precise formation of openings with smaller aspect ratios, thus minimizing parasitic capacitance and enhancing mechanical strength.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the gate length is reduced to achieve smaller aspect ratios for opening formation, then the manufacturing precision improves, but the electrical resistance of the gate electrode increases adversely affecting high-frequency signals

Engineering Contradiction:
Improveopening formation precisionVSAvoidhigh-frequency signal characteristics
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The gate electrode is divided into multiple segments (first gate electrode and second gate electrode) separated by an insulating film. This segmentation allows each segment to be independently optimized for electrical performance while maintaining manufacturable dimensions, thereby reducing the adverse effect of electrical resistance on high-frequency signals without compromising opening formation precision

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An insulating film is introduced as an intermediary between the first and second gate electrodes. This intermediary structure enables the gate to be split into multiple parts that can be formed with standard aspect ratios, improving manufacturability while the overall gate structure maintains low electrical resistance for high-frequency operation

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If the gate electrode structure is simplified to ease manufacturing, then the ease of manufacture improves, but the mechanical strength and high-frequency characteristics deteriorate

Engineering Contradiction:
Improvegate electrode fabricationVSAvoidmechanical strength and high-frequency performance
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The gate electrode is segmented into multiple parts with an insulating film between them, which simplifies the fabrication process by allowing standard opening formation techniques to be used. At the same time, the segmented structure maintains mechanical strength and optimizes high-frequency characteristics by reducing parasitic effects and electrical resistance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate structure uses a composite configuration combining conductive gate electrode materials with insulating film materials. This composite structure achieves both ease of manufacture (through standard fabrication processes) and high mechanical strength with optimized high-frequency performance

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS20240162340A1Semiconductor device and manufacturing method
Publication Date: 2024.05.16 1FINITY INC
  • US20240162340A1 patent drawing
  • US20240162340A1 patent drawing
  • US20240162340A1 patent drawing

AI summary

A semiconductor device includes a semiconductor layer including an electron transit layer and an electron supply layer; a gate electrode, a source electrode and a drain electrode, the gate electrode, the source electrode and the drain electrode being disposed on the semiconductor layer; and a metal film connected to the gate electrode, wherein the semiconductor layer includes an active region, and an inactive region surrounding the active region in plan view, wherein the gate electrode includes, in plan view, a first region overlapping the active region, and two second regions having the first region interposed therebetween, the two second regions both overlapping the inactive region, and wherein the metal film contacts the two second regions.