HEMT Gate Sidewall Passivation for Leakage Reduction

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Solution Overview

Problem

GaN HEMT devices with AlGaN/GaN schottky barriers and p-GaN gates suffer from high gate leakage due to process-induced traps and damage, leading to degraded device performance, as they tend to operate in depletion mode rather than enhancement mode.

Innovation Solution

A passivation layer, such as aluminum nitride (AlN) or boron nitride (BN), is formed conformally over the gate sidewalls and upper surface to terminate dangling bonds and reduce interfacial traps, thereby minimizing gate leakage and enhancing device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a passivation layer is formed conformally over the gate sidewalls and upper surface, then gate leakage current is reduced significantly, but device complexity increases due to additional manufacturing steps

Engineering Contradiction:
Improvegate leakage currentVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The passivation layer is formed conformally over the gate sidewalls and upper surface before final device assembly, preventing trap formation and gate leakage in advance. This preliminary protective action eliminates the need for subsequent gate leakage mitigation steps, resolving the contradiction between reliability improvement and manufacturing complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The passivation layer acts as an intermediary between the gate structure and the environment, terminating dangling bonds and blocking harmful interactions that cause gate leakage. This intermediary layer simplifies the overall device structure by consolidating multiple protective functions into a single component.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the HEMT device operates in depletion mode with AlGaN/GaN schottky barriers, then device performance is degraded due to high gate leakage, but switching to enhancement mode requires additional structural modifications

Engineering Contradiction:
Improvedevice performanceVSAvoidstructural modification complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention changes the operational parameter of the device from depletion mode to enhancement mode by introducing the passivation layer that enables proper gate control. This parameter change improves device performance by eliminating gate leakage without requiring fundamental structural redesign, as the passivation layer integrates seamlessly with existing AlGaN/GaN heterostructure.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The passivation layer significantly reduces gate leakage current by approximately an order of magnitude, improving the operational efficiency and switching characteristics of the HEMT devices, allowing them to function in enhancement mode with reduced trap-induced degradation.

Implementation Method 1

the first conformal passivation layer terminates and passivates dangling bonds on the surface of gate sidewall surfaces to limit the number of interfacial traps

Methodology Applied
Scientific EffectSurface passivation:

Data Source

PatentUS11522066B2Sidewall passivation for HEMT devices
Publication Date: 2022.12.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11522066B2 patent drawing
  • US11522066B2 patent drawing
  • US11522066B2 patent drawing

AI summary

Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.